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公开(公告)号：KR1019960019656A
公开(公告)日：1996-06-17
申请号：KR1019940030900
申请日：1994-11-23
IPC: H01L21/76
Abstract: 본 발명은 반도체 장치에서 각 트렌지스터내의 활성영역과 필드영역을 격리(isolation)시키는 방법에 관한 것으로서, 특히 저심도랑(shallow trench)를 이용하여 LOCOS(Local Oxidation of Silicon)의 버즈-빅(Bird′s Beak)을 제거한 소자 격리방법에 관한 것이다.
본 발명의 제1실시예에 따르면, 소자의 활성영역이 측면질화막 패턴에 의한 절연막으로 채워진 도랑(insulator-filled trench)을 이용하여 격리된다.
본 발명의 제2실시예에 의하면 트렌치 식각(trench etchning) 공정에 의한 트렌치 패턴에 의해 버즈-빅이 없이 필드영역을 격리시킬 수 있다.-
公开(公告)号：KR1019960003851B1
公开(公告)日：1996-03-23
申请号：KR1019920023355
申请日：1992-12-04
Applicant: 한국전자통신연구원
IPC: H01L21/336
Abstract: The title method comprises (A) forming a dielectric thin film(2) on a semiconductor substrate(1), (B) coating the thin film(2) with a photoresist(3) and forming patterns, (C) etching the exposed dielectric thin film(2) on the tilt with respect to the substrate(1), (D) forming a gate(7) on the exposed substrate(1), while forming a gate metal(6) on the photoresist film(3) on the opposite tilt to the etching tilt by electronic beam heating, (E) remaining only the gate(7) by etching the gate metal(6), the photoresist film(3) and the dielectric thin film(2) by turn, and (F) forming a source electrode(9), a drain electrode(10) and a gate electrode by forming an ohmic metal(8) with the patterned photoresist film(3a).
Abstract translation: 标题方法包括：（A）在半导体衬底（1）上形成电介质薄膜（2），（B）用光致抗蚀剂（3）涂覆薄膜（2）并形成图案，（C）蚀刻暴露的电介质 相对于基板倾斜的薄膜（2），（D）在曝光的基板（1）上形成栅极（7），同时在光致抗蚀剂膜（3）上形成栅极金属（6） 通过电子束加热与蚀刻倾斜相反的倾斜，（E）仅通过蚀刻栅极金属（6），光致抗蚀剂膜（3）和电介质薄膜（2）而仅剩下栅极（7），并且（ F）通过与图案化的光致抗蚀剂膜（3a）形成欧姆金属（8）形成源电极（9），漏电极（10）和栅电极。
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公开(公告)号：KR1019960003850B1
公开(公告)日：1996-03-23
申请号：KR1019920023357
申请日：1992-12-04
Applicant: 한국전자통신연구원
IPC: H01L21/335
Abstract: The compound semiconductor device, which forms electric channel by activating a gallium arsenide substrate(10) implanted with ions, is composed of (A) forming an aluminum arsenide layer(30) and gallium arsenide layer(40) on a gallium arsenide substrate(10) where an ion implanted layer(20) is formed by epitaxial method, (B) forming a silica layer(50) on the gallium arsenide layer(40) by PECVD method, (C) heat-treating the substrate(10) at elevated temperature, and (D) etching the silica layer(50), gallium arsenide layer(40) and aluminum arsenide layer(30). When the silica layer(50) is etched, the buffer oxide film etchant is used.
Abstract translation: 通过激活注入离子的砷化镓衬底（10）形成电通道的化合物半导体器件由（A）在砷化镓衬底（10）上形成砷化铝层（30）和砷化镓层（40） ），其中通过外延法形成离子注入层（20），（B）通过PECVD法在所述砷化镓层（40）上形成二氧化硅层（50），（C）在升高的温度下对所述衬底（10）进行热处理 温度，和（D）蚀刻二氧化硅层（50），砷化镓层（40）和砷化铝层（30）。 当蚀刻二氧化硅层（50）时，使用缓冲氧化物膜蚀刻剂。
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公开(公告)号：KR1019950011015B1
公开(公告)日：1995-09-27
申请号：KR1019920025021
申请日：1992-12-22
Applicant: 한국전자통신연구원
IPC: H01L21/08
Abstract: The method consists of a step of forming a boding thin film on a silicon substrate, a step of forming a polycrystalline silicon layer on the thin film, a step of flattening the surface of the polycrystalline silicon layer, and a step of removing the silicon substrate after bonding a semiconductor substrate with the semiconductor substrate with the flattened polycrystalline silicon layer.
Abstract translation: 该方法包括在硅衬底上形成掺杂薄膜的步骤，在薄膜上形成多晶硅层的步骤，使多晶硅层的表面变平的步骤以及去除硅衬底的步骤 在将半导体衬底与半导体衬底与扁平多晶硅层接合之后。
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公开(公告)号：KR1019950009638B1
公开(公告)日：1995-08-25
申请号：KR1019920026629
申请日：1992-12-30
Applicant: 한국전자통신연구원
IPC: H01L41/27
Abstract: joining a first substrate including a thermal oxide film(8) fromed on an n- silicon substrate(1) and a second sustrate including a p- epitaxy layer(7) formed on a p++ silicon substrate(10) so as to bring the thermal oxide film(8) and the epitaxy layer(7) together; joining a third substrate formed by etching the p++ silicon substrate(10) and a fourth sustrate including a piezoresistor(2) and a dielectrics separating oxide film(9) formed on a silicon substrate(1a) so as to bring the epitaxy layer(7) and the dielectrics separating oxide film(9) together; etching the silicon substrate(1a) using a first silicon film(13) as a mask; forming an electrode(4) on the piezoresistor, and forming a passivation oxide film(14) and a second silicon film(13a) on the dielectrics separating oxide film(9) in turn; forming a diaphragm pattern of the silicon films(13)(13a); and forming a thin silicon diaphragm(3) by etching the n- silicon substrate(1). The method can improve an output response chracteristic to temperature, product the homogeneous diaphragm, and control the thickness of the diaphragm.
Abstract translation: 接合包括从n型硅衬底（1）上的热氧化膜（8）的第一衬底和包括形成在p ++硅衬底（10）上的p-外延层（7）的第二衬垫，以使热 氧化膜（8）和外延层（7）; 接合通过蚀刻p ++硅衬底（10）形成的第三衬底和包括形成在硅衬底（1a）上的压电电阻（2）和电介质分离氧化膜（9）的第四衬底，以使外延层（7） ）和将氧化物膜（9）分离在一起的电介质; 使用第一硅膜（13）作为掩模蚀刻硅衬底（1a）; 在所述压电电阻器上形成电极（4），并依次在所述电介质隔离氧化膜（9）上形成钝化氧化膜（14）和第二硅膜（13a） 形成硅膜（13）（13a）的光阑图案。 以及通过蚀刻所述n型硅衬底（1）形成薄的硅膜（3）。 该方法可以提高温度特性，产生均匀膜片，控制膜片厚度的输出响应。
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Patent Agency Ranking
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公开(公告)号：KR1019940016454A
公开(公告)日：1994-07-23
申请号：KR1019920023357
申请日：1992-12-04
Applicant: 한국전자통신연구원
IPC: H01L21/335
Abstract: 본 발명은 갈륨비소 화합물 반도체의 이온주입(Ion Implantation)공정, 분자선 에피성장(Molecular Beam Epitaxy : MBE) 및 플라즈마 화학증착법(Plasma Enhanced Chemical Vapor Deposition : PECVD)을 기초로 하여 이온주입된 갈륨비소층을 활성화시키는 화합물 반도체 소자의 제조방법에 관한 것으로, 이온주입되어 이온주입층(20)이 형성된 갈륨비소 기판(10)을 활성화 하여 전기적 채널을 형성하는 화합물 반도체 소자의 제조방법에 있어서, 상기 이온주입층(20)이 형성된 갈륨비소 기판(10)상에 알루미늄 비소층(30)과 갈륨비소층(40)을 에피택셜 공정에 의해 성장하는 공정과, 상기 갈륨비소층(40)상에 PECVD을 이용하여 SiO
2 층(50)을 형성하는 공정과, 상기 기판(10)을 고온 열처리 하는 공정과, 상기 SiO
2 층(50)과 갈륨비소층(40) 및 알루미늄 비소층(30)을 식각하는 공정을 포함한다.-
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公开(公告)号：KR1019940004262B1
公开(公告)日：1994-05-19
申请号：KR1019900021813
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/335
Abstract: preparing a GaAs substrate; depositing a Si layer on the substrate; forming a first photoresist pattern on the Si layer; etching the Si layer using the first photoresist pattern as a mask to define ohmic contact regions of source/drain electrodes; forming a second photoresist pattern on the substrate after removal of the first photoresist pattern to define a channel region and injecting a predetermined quantity of Si ions into the substrate; depositing a protective layer around the substrate after removal of the second photoresist pattern; and annealing the substrate to activate Si ions of the remaining Si layer and diffusing the activating Si ions into the deep direction of the substrate.
Abstract translation: 制备GaAs衬底; 在衬底上沉积Si层; 在所述Si层上形成第一光刻胶图案; 使用第一光致抗蚀剂图案作为掩模蚀刻Si层以限定源/漏电极的欧姆接触区域; 在去除第一光致抗蚀剂图案之后在衬底上形成第二光致抗蚀剂图案以限定沟道区域并将预定量的Si离子注入到衬底中; 在除去第二光致抗蚀剂图案之后，在衬底周围沉积保护层; 并且使衬底退火以激活剩余Si层的Si离子并将活化Si离子扩散到衬底的深度方向。
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公开(公告)号：KR1019940002397B1
公开(公告)日：1994-03-24
申请号：KR1019910010539
申请日：1991-06-25
Applicant: 한국전자통신연구원
IPC: H01L29/73
Abstract: The metallic semiconductor transistor production processes comprise: (a) plasma enhanced chemical vapor deposition of silicon nitride (or silicon dioxide as an insulating material for enhancing breakdown and threshold voltages) (6) having a source and a drain (5), forming a photosensitive film (7) having an over-hang structure at a gate part by curing the photosensitive film with monochlorobenzene, dry etching silicon nitirde exposed at a gate (8) part, and wet etching (the 1st self aligned recess) gallium arsenide layer of N positive layer (4); (b) lateral etching by dry etching silicon nitride under the photosensitive film; (c) wet etching (the 2nd or wide recess) the N negative (3) and N positive (4) layers with silicon nitride as a mask; (d) after vacuum depositing metal for the gate, removing the photosensitive film with an organic component remover, acetone etc., and eliminating the metallic layer deposited on the photosensitive film.
Abstract translation: 金属半导体晶体管的制造方法包括：（a）具有源极和漏极（5）的氮化硅（或二氧化硅作为用于增强击穿和阈值电压的绝缘材料）的等离子体增强化学气相沉积，形成光敏 通过用一氯苯固化感光膜，在栅极部分具有过悬挂结构的膜（7），在栅极（8）部分暴露的干蚀刻硅氮化物，以及N（N第一自对准凹槽）砷化镓层 正层（4）; （b）通过在感光膜下干蚀刻氮化硅进行横向蚀刻; （c）用氮化硅作为掩模的N阴性（3）和N（4）层的湿蚀刻（第二或宽凹槽） （d）真空沉积金属为栅极，用有机成分去除剂丙酮等去除感光膜，并消除沉积在感光膜上的金属层。
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