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    ELECTRICAL CONNECTOR SYSTEM WITH ORTHOGONAL CONTACT TAILS
    112.
    发明申请
    ELECTRICAL CONNECTOR SYSTEM WITH ORTHOGONAL CONTACT TAILS 审中-公开
    具有正交接触尾部的电气连接器系统

    公开(公告)号：WO2009061655A3

    公开(公告)日：2009-07-23

    申请号：PCT/US2008081699

    申请日：2008-10-30

    Applicant: FRAMATOME CONNECTORS INT ,  FCI AMERICAS TECHNOLOGY INC ,  JOHNESCU DOUGLAS M ,  MINICH STEVEN ,  SMITH STEPHEN B

    Inventor： JOHNESCU DOUGLAS M ,  MINICH STEVEN ,  SMITH STEPHEN B

    IPC: H01R12/16

    CPC classification number: H01R13/6471 ,  H01R12/51 ,  H01R12/7082 ,  H01R12/71 ,  H01R13/514 ,  H01R13/6477 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/325 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10189 ,  H05K2201/1059 ,  Y10T29/49222

    Abstract: Disclosed are electrical connectors and methods of assembling an electrical connector having "standard" (i.e., with electrical contacts having in-line tails), jogged (i.e., with electrical contacts having jogged tails but not connected orthogonally to another connector through a substrate), and/or "orthogonal" (i.e., with electrical contacts having jogged tails that are used in an orthogonal application) leadframe assemblies in the same connector. This provides the flexibility of using some of the available contacts in an orthogonal application and, at the same time, having remaining contacts available for routing on the midplane PCB. Though this could be done using only orthogonal leadframe assemblies, the combination of standard leadframe assemblies with orthogonal leadframe assemblies creates additional spacing between the PCB vias, so that signal traces can be more easily routed on the midplane PCB.

    Abstract translation: 公开了电连接器和组装电连接器的方法，即具有“标准”（即，具有线内尾部的电触头）的电连接器，具有点动的（即，具有慢跑尾部的电触点但未通过基板与另一个连接器正交连接） 和/或“正交”（即，具有在正交应用中使用的具有慢跑尾部的电触头）引线框组件在同一连接器中。 这提供了在正交应用中使用一些可用触点的灵活性，并且同时具有可用于在中板PCB上布线的剩余触点。 尽管这可以仅使用正交引线框架组件完成，标准引线框架组件与正交引线框架组合的组合在PCB通孔之间产生额外的间隔，从而可以更容易地在中板PCB上布线信号迹线。

    METHOD AND APPARATUS FOR CONFIGURABLE CIRCUITRY
    113.
    发明申请
    METHOD AND APPARATUS FOR CONFIGURABLE CIRCUITRY 审中-公开
    用于配置电路的方法和装置

    公开(公告)号：WO2006034374A3

    公开(公告)日：2007-11-15

    申请号：PCT/US2005033896

    申请日：2005-09-22

    Applicant: DIGI INT INC

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  H05K1/0206 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/111 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/0064 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124

    Abstract: At (1502) is a digital input, at (1504) an external I/O, and at (1506) an analog or digital output, and at (1508) a test point. Also as indicated are positions for resistors: R1, R2A, R2B, R3A, R3B, R4A, R4B, R5, R6, R7; and capacitor: C1. Also shown are transistor. Q1, +5V,+3.3V, and ground. At the locations indicated are where the schematic entries in Figure 15A may be placed. A plus inside a trace denotes the +5V supply, and a minus inside a trace denotes ground. For example, if resistive components can only be placed horizontally, then padsassociated with R2B, R5, and R6 may be repositioned.

    Abstract translation: 在（1502）是（1504）外部I / O以及（1506）模拟或数字输出以及（1508）测试点的数字输入。 此外，如图所示，电阻器的位置：R1，R2A，R2B，R3A，R3B，R4A，R4B，R5，R6，R7; 和电容C1。 还示出了晶体管。 Q1，+ 5V，+ 3.3V，接地。 在所示的位置处可以放置图15A中的原理图条目。 轨迹内的加号表示+ 5V电源，迹线内的减号表示接地。 例如，如果电阻性元件只能水平放置，则可以重新定位与R2B，R5和R6相关联的焊盘。

    MONOLITHIC MULTI-LEVEL MODULE AND METHOD
    114.
    发明申请
    MONOLITHIC MULTI-LEVEL MODULE AND METHOD 审中-公开
    单片多级模块和方法

    公开(公告)号：WO2006057729A2

    公开(公告)日：2006-06-01

    申请号：PCT/US2005037159

    申请日：2005-10-18

    Applicant: INTRAGLOBAL CORP ,  GREGORY JOHN

    Inventor： GREGORY JOHN

    IPC: H05K1/16

    CPC classification number: H05K3/303 ,  H01L23/49572 ,  H01L2924/0002 ,  H05K3/3421 ,  H05K2201/09418 ,  H05K2201/10568 ,  H05K2201/10681 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00

    Abstract: An interposer having a substrate composed of a flat flexible thin sheet of plastic dielectric material having a copper film laminated on one side. The substrate defines a component site in the form of a cavity in the substrate. The copper film defines a plurality of separated interconnects, each having a tab extending into the cavity formed in the substrate. An electrical component having contacts is positioned in the cavity and its contacts are bonded to the tabs. At least a plurality of the separate interconnects extend laterally beyond the substrate to define flanges. The substrate is profiled to be easily oriented in a PCB. A monolithic multi-level micropackage having a plurality of layers of copper foils laminated on flexible thin substrates processed to embed in at least one layer an interposer according to the above, the layers being bonded together by a bonding material and compressed to form a monolithic structure. The monolithic structure can have geometry to enable easy registration in a PCB. The geometry can be cylindrical with protrusions. The top layer can define connecting flanges to connect with leads on the PCB. Heat sinks can be incorporated into the structure.

    Abstract translation: 具有由具有层叠在一侧的铜膜的塑料电介质材料的扁平柔性薄片构成的基板的插入体。 衬底限定了衬底中空腔形式的部件位置。 铜膜限定了多个分离的互连件，每个互连件具有延伸到形成在基板中的空腔中的突出部。 具有触点的电气部件定位在空腔中，并且其触点被接合到突出部。 至少多个单独的互连件横向延伸超出基板以限定凸缘。 基板被成型为易于在PCB中取向。 一种具有多层铜箔的单片多层微封装层叠在柔性薄基板上，被加工成至少一层嵌入至少一层中间层，该层通过粘接材料粘结在一起，并压制成整体结构 。 单片结构可以具有几何形状以便于在PCB中轻松配准。 几何形状可以是具有突起的圆柱形。 顶层可以定义连接法兰以连接PCB上的引线。 散热器可以结合到结构中。

    光モジュール及び光送受信装置
    115.
    发明申请
    光モジュール及び光送受信装置 审中-公开
    光学模块和光传输/接收设备

    公开(公告)号：WO2004079876A1

    公开(公告)日：2004-09-16

    申请号：PCT/JP2004/002870

    申请日：2004-03-05

    Applicant: 松下電器産業株式会社 ,  佐藤 吉保 ,  東郷 仁麿 ,  浅野 弘明

    Inventor： 佐藤 吉保 ,  東郷 仁麿 ,  浅野 弘明

    IPC: H01S5/022

    CPC classification number: H05K3/306 ,  G02B6/3604 ,  G02B6/4206 ,  H01S5/02212 ,  H01S5/02284 ,  H05K2201/09418 ,  H05K2201/09809 ,  H05K2201/10121

    Abstract: 光モジュールを構成する光素子の光ファイバ円周方向の角度に影響を受けることなく、光素子の電極を配線基板に実装する際の自由度を高める技術が開示され、その技術によれば複数の電極６１～６４が突出した光素子５と、複数の電極の各々とを接続するための複数の電気配線１０が略同心円状に形成された配線基板７を備え、複数の電極の各先端と光素子の中心との距離が異なるように電極の各先端をそれぞれ複数の電気配線の各々に接続する。

    Abstract translation: 一种增加在印刷电路板上安装光学元件的电极的自由度的技术。 这可以在不受构成光学模块的光学元件的光纤的圆周方向的角度的影响的情况下实现。 该技术的光学模块具有投射电极（61-64）的光学元件（5）和用于使各个电极之间连接的电线（10）基本上同心地布置在其上的电路板（7） 圆形 电极的每个端部连接到每根电线，使得电极的每个端部与光学元件的中心之间的距离变化。

    配線基板及びその半田付け方法
    116.
    发明申请
    配線基板及びその半田付け方法 审中-公开
    接线板及其焊接方法

    公开(公告)号：WO2002089544A1

    公开(公告)日：2002-11-07

    申请号：PCT/JP2002/004293

    申请日：2002-04-26

    Applicant: 栗山 厚子 ,  栗山 達也 ,  中井 満久 ,  京極 章弘 ,  中本 善直 ,  谷口 幸次 ,  東 博明

    Inventor： 中井 満久 ,  京極 章弘 ,  中本 善直 ,  谷口 幸次 ,  東 博明

    IPC: H05K3/34

    CPC classification number: H05K3/3468 ,  H05K1/111 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09418 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/611

    Abstract: A wiring board is characterized by comprising a first solder pulling land (13a) adjacent to the tail mounting land that is the last land in the direction in which the board is moved when an electronic componed is soldered by wave soldering and a second solder pulling land (13b) behind the first solder pulling land (13a) in the direction in which the board is moved. When a component having leads the pitches of which are narrow, represented by a QFPIC, is soldered by wave soldering, any solder bridge formed of surplus solder staying at the last lead and lands is hardly produced. The wiring board is suitable for use of solder not containing lead, thereby contributing to the environment protection.

    Abstract translation: 布线板的特征在于包括：当电子部件通过波峰焊接焊接时，邻近尾部安装台面的第一焊料拉动焊盘（13a），该焊接区域是板移动方向上的最后一个焊盘，第二焊料拉动焊盘 （13b）沿着所述板移动的方向在所述第一焊料拉动区域（13a）的后面。 当通过波峰焊接焊接由QFPIC表示的间距窄的部件被焊接时，几乎不产生由留在最后引线和焊盘上的剩余焊料形成的任何焊料桥。 接线板适用于不含铅的焊料，有助于环保。

    IMPROVED THREE-DIMENSIONAL CIRCUIT COMPONENT ASSEMBLY AND METHOD CORRESPONDING THERETO
    117.
    发明申请
    IMPROVED THREE-DIMENSIONAL CIRCUIT COMPONENT ASSEMBLY AND METHOD CORRESPONDING THERETO 审中-公开
    改进的三维电路组件组件及其相关方法

    公开(公告)号：WO1990015478A2

    公开(公告)日：1990-12-13

    申请号：PCT/US1990002757

    申请日：1990-05-18

    Applicant: TROVE TECHNOLOGY, INC.

    Inventor： TROVE TECHNOLOGY, INC. ,  BERHOLD, G., Mark

    IPC: H03D0

    CPC classification number: H05K1/189 ,  H05K1/144 ,  H05K3/3447 ,  H05K7/023 ,  H05K2201/046 ,  H05K2201/09018 ,  H05K2201/09418 ,  H05K2201/10515

    Abstract: A plurality of plate-like circuit component carrier packages (71) are stacked adjacent one to another with the flat faces (72, 74) thereof in contact to form a carrier package assembly (40). Each carrier package houses one or more electrical circuit component (110) coupled to electrical contacts (84, 86) on the flat faces and electrical contacts (98) or upstanding pins (424, 436) on the sides. These cooperate with those of adjacent carrier packages to electrically interconnect with the circuit components therein. A flexible, printed circuit board (50) having an array of contact sites (52) selectively interconnected by printed routing traces (54) is wrapped around the carrier package assembly. The ends of the carrier package assembly are fitted with supporting and electrically interconnecting connector blocks (22, 16). Plural carrier package assemblies are interconnectable directly, by nesting, or through intermediate connecting structures.

    Abstract translation: 多个板状电路部件载体封装（71）彼此相邻地堆叠，其平面（72,74）接触形成载体封装组件（40）。 每个载体封装容纳一个或多个耦合到平面上的电触头（84,86）和电触头（98）或两侧的直立插脚（424,436）的电路部件（110）。 这些与相邻载体封装件的配合与其中的电路部件电互连。 具有通过打印的布线迹线（54）选择性互连的接触位置阵列的柔性印刷电路板（50）被卷绕在载体封装组件上。 载体封装组件的端部装配有支撑和电互连的连接器块（22,16）。 多个载体包装组件可通过嵌套或通过中间连接结构互连。

    THREE-DIMENSIONAL CIRCUIT COMPONENT ASSEMBLY AND METHOD CORRESPONDING THERETO
    118.
    发明申请
    THREE-DIMENSIONAL CIRCUIT COMPONENT ASSEMBLY AND METHOD CORRESPONDING THERETO 审中-公开
    三维电路组件组件及其相关方法

    公开(公告)号：WO1989007382A1

    公开(公告)日：1989-08-10

    申请号：PCT/US1989000184

    申请日：1989-01-17

    Applicant: BERHOLD, G., Mark

    IPC: H05K01/00

    CPC classification number: H05K1/189 ,  H05K3/3447 ,  H05K7/023 ,  H05K2201/046 ,  H05K2201/09018 ,  H05K2201/09418 ,  H05K2201/10515

    Abstract: A plurality of circuit component carrier packages (71) having the same size and shape are stacked adjacent one to another with the faces (72, 74) thereof in contact to form a carrier package assembly (40) in the form of a prismatic or cylindrical solid. Each carrier package houses one or more electrical circuit components (110) and is provided at portions of the faces thereof with electrical contacts (84, 86) which cooperate with similarly located contacts on the faces of adjacent carrier packages to electrically interconnect the circuit components. The carrier package assembly is usable with a flexible, printed circuit board (50) having on one side thereof an array of contact sites (52) selectively interconnected by printed routing traces (54). Electrical contacts on the peripheral surfaces of the carrier packages are coupled with the circuit components housed therein and engage the contact sites on the circuit board when it is wrapped around the carrier package assembly.

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