公开(公告)号：KR1020100092240A

公开(公告)日：2010-08-20

申请号：KR1020090011526

申请日：2009-02-12

Applicant: 삼성전자주식회사

Inventor： 김영옥 ,  한정남 ,  홍창기 ,  윤보언 ,  이근택 ,  김영후

IPC: H01L21/66

CPC classification number: H01L22/14

Abstract: PURPOSE: The wafer testing method and wafer inspection system measure the electric resistance of the second between electrode which is close with the electrolyte and the first electrode which is electrically close with the containing film pattern. The corrosion index is grasped. CONSTITUTION: The wafer(W) including the chip area in which the metal film pattern(60) is formed is prepared. In the lower part and top of the metal film pattern, oxides locate. In the chip area, the electrolyte(112) is provided in order to be close with the task part of the metal film pattern. The electric resistance of the second between electrode which is close with the first electrode and electrolyte is measured at. The first electrode is electrically connected to the other part of the metal film pattern.

Abstract translation: 目的：晶片测试方法和晶片检测系统测量与电解质接近的电极之间的第二电极和与含有膜图案电气接近的第一电极的电阻。 了解腐蚀指标。 构成：制备包括其中形成有金属膜图案（60）的芯片区域的晶片（W）。 在金属膜图案的下部和顶部，氧化物定位。 在芯片区域中，提供电解质（112）以便与金属膜图案的任务部分接近。 测量与第一电极和电解质接近的电极之间的第二电极的电阻。 第一电极电连接到金属膜图案的另一部分。

公开(公告)号：KR1020100092226A

公开(公告)日：2010-08-20

申请号：KR1020090011506

申请日：2009-02-12

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  홍창기 ,  최재형 ,  손윤호 ,  박민영 ,  탁용석

IPC: H01L21/28 ,  H01L21/324

CPC classification number: H01L21/76877 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76883

Abstract: PURPOSE: In the oxygen atmosphere the tungsten contact plug, it processes R T A. The manufacturing method of the semiconductor device restored the tungsten plug processed R T O in the hydrogen atmosphere processes the tungsten oxides in the hydrogen atmosphere of the high temperature RTH. CONSTITUTION: The contact hole is formed in the insulating layer(120). The tungsten(V) is on the insulating layer the chemical vapor deposition. The chemical vapor deposition operates to the one-step. The tungsten is the chemical mechanical polishing and the tungsten contact plug(140) is formed. In the oxygen atmosphere, the tungsten contact plug is the rapid thermal processing.

Abstract translation: 目的：在氧气氛中，钨接触塞处理R T A.在氢气氛中，半导体器件恢复钨硅处理的R T O的制造方法在高温RTH的氢气气氛中处理钨氧化物。 构成：接触孔形成在绝缘层（120）中。 钨（V）在绝缘层上是化学气相沉积。 化学气相沉积操作为一步。 钨是化学机械抛光，形成钨接触塞（140）。 在氧气氛中，钨接触插塞是快速热处理。

公开(公告)号：KR1020100053393A

公开(公告)日：2010-05-20

申请号：KR1020080130438

申请日：2008-12-19

Applicant: 삼성전자주식회사

Inventor： 박임수 ,  김영후 ,  홍창기 ,  이재동 ,  엄대홍 ,  김성준

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/0688 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/11578 ,  H01L27/2463

Abstract: PURPOSE: A method for fabricating a nonvolatile memory device and the nonvolatile memory device fabricated thereby are provided to improve the reliability of the device by preventing the loss of electrical charges. CONSTITUTION: A plurality of layers which is based on materials with different etching selectivity is alternately stacked on a semiconductor substrate(100). An opening passes through the layers. Expansion parts which are expanded from the opening are formed in a horizontal direction to the semiconductor substrate. An electrical charge trapping layer is conformally formed along the surface of the opening and the expanding parts. Patterns(142) of the electrical charge trapping layer are locally formed in the expansion parts.

Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法和由此制造的非易失性存储器件，以通过防止电荷损失来提高器件的可靠性。 构成：基于具有不同蚀刻选择性的材料的多个层交替堆叠在半导体衬底（100）上。 一个开口穿过这些层。 从开口部扩展的膨胀部在与半导体基板的水平方向形成。 电荷捕获层沿着开口的表面和扩展部分共形地形成。 电荷捕获层的图案（142）局部形成在膨胀部分中。

公开(公告)号：KR1020090054552A

公开(公告)日：2009-06-01

申请号：KR1020070121269

申请日：2007-11-27

Applicant: 삼성전자주식회사

Inventor： 김유경 ,  이근택 ,  심우관 ,  홍창기

IPC: H01L21/335

CPC classification number: H01L21/31144 ,  H01L21/30617 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/6653

Abstract: A method for forming a sidewall spacer and a method for manufacturing a semiconductor device using the same are provided to reduce damage in a lower layer by forming the spacer through a wet etch process. A pattern structure(108) is formed on a substrate(100). An insulating layer(110) for a spacer is formed on a surface of the pattern structure and a substrate surface. A sacrificial layer(112) is formed in the insulating layer for the spacer. The sacrificial layer is formed in a sidewall of the pattern structure by wet-etching the sacrificial layer. The spacer is formed in the side wall of the pattern structure by removing the exposed insulation layer for the spacer and the sacrificial layer pattern while remaining the insulation layer for the spacer covered with the sacrificial layer pattern.

Abstract translation: 提供一种用于形成侧壁间隔物的方法和使用其制造半导体器件的方法，以通过湿式蚀刻工艺形成间隔物来减少下层的损伤。 图案结构（108）形成在基板（100）上。 在图案结构的表面和基板表面上形成用于间隔件的绝缘层（110）。 在间隔物的绝缘层中形成牺牲层（112）。 通过湿蚀刻牺牲层，在图案结构的侧壁中形成牺牲层。 通过除去用于间隔物的暴露的绝缘层和牺牲层图案，同时保留用牺牲层图案覆盖的间隔物的绝缘层，形成间隔物在图案结构的侧壁中。

公开(公告)号：KR100894985B1

公开(公告)日：2009-04-24

申请号：KR1020070065615

申请日：2007-06-29

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  한상엽 ,  홍창기 ,  윤보언 ,  이재동

IPC: C09K3/14

CPC classification number: C23F3/00 ,  C09G1/02

Abstract: 금속 연마용 슬러리 조성물, 이를 이용한 금속 대상체의 연마 방법 및 금속 배선의 형성 방법에 있어서, 금속 연마용 슬러리 조성물은 탄소 사슬의 측쇄에 술폰산 이온(SO
3
- ) 및 설페이트 이온(OSO
3
- ) 중에서 선택되는 적어도 하나의 음이온을 포함하는 고분자성 연마속도 향상제 및 산성수용액을 포함한다. 금속 연마용 슬러리 조성물은 연마 대상체에 대하여 높은 연마 속도와 낮은 부식력을 지니고 있어 반도체 제조 공정의 효율 및 수율을 향상시킬 수 있다.

公开(公告)号：KR1020090010809A

公开(公告)日：2009-01-30

申请号：KR1020070074206

申请日：2007-07-24

Applicant: 삼성전자주식회사

Inventor： 엄대홍 ,  홍창기 ,  심우관 ,  김영옥

IPC: H01L21/304

CPC classification number: B08B3/04 ,  B08B3/10 ,  H01L21/67034 ,  H01L21/67051

Abstract: A method for substrate transaction is provided to improve dry characteristic by suppressing generation of a water mark and controlling the rotation speed of a wafer in drying. A method for substrate transaction is comprised of steps: rinsing a substrate surface with hyper-pure water; supplying a dry gas to the substrate and drying it(s30). The substrate is rotated to the low velocity less than 50rpm in drying process. A water film is formed before the dry gas is supplied to the surface of the substrate, and the dry gas is moved to the edge of the substrate while the substrate having the water film.

Abstract translation: 提供了一种基板交易方法，通过抑制水印的产生和控制晶片在干燥中的转速来提高干燥特性。 底物交易的方法包括以下步骤：用超纯水冲洗底物表面; 向基材供应干燥气体并干燥（s30）。 在干燥过程中将基材旋转到低于50rpm的低速。 在将干燥气体供给到基板的表面之前，形成水膜，在具有水膜的基板的同时，将干燥气体移动到基板的边缘。

公开(公告)号：KR1020090006436A

公开(公告)日：2009-01-15

申请号：KR1020070069783

申请日：2007-07-11

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  백인규 ,  임종흔 ,  홍창기 ,  윤보언

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/28273 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/2463

Abstract: The non-volatile semiconductor memory device and manufacturing method thereof are provided to reduce the area of variable resistance patterns by overlapping partially the bottom electrodes and the bit lines. The contact hole(306) is formed on the first interlayer insulating film(304). The photoresist pattern is formed on the second inter metal dielectric(316). The spacer(352) is formed on the side wall of photoresist patterns. After photoresist patterns are removed, the second inter metal dielectric is etched and the second inter metal dielectric groove(354) is formed. After spacers are removed, the variable resistance pattern(318) and bit line(320) are formed.

Abstract translation: 提供非易失性半导体存储器件及其制造方法，以通过部分地重叠底部电极和位线来减小可变电阻图案的面积。 接触孔（306）形成在第一层间绝缘膜（304）上。 光致抗蚀剂图案形成在第二金属间电介质（316）上。 间隔物（352）形成在光刻胶图案的侧壁上。 在除去光致抗蚀剂图案之后，蚀刻第二金属间电介质并形成第二金属间介电槽（354）。 在移除间隔物之后，形成可变电阻图案（318）和位线（320）。

公开(公告)号：KR1020090001334A

公开(公告)日：2009-01-08

申请号：KR1020070065615

申请日：2007-06-29

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  한상엽 ,  홍창기 ,  윤보언 ,  이재동

IPC: C09K3/14

CPC classification number: C23F3/00 ,  C09G1/02

Abstract: A slurry composition for polishing metals is provided to improve the efficiency and yield of semiconductor manufacture due to high polishing speed and low corrosion to an object for polishing. A slurry composition for polishing metals comprises a polymeric polishing speed improver and acidic aqueous solution, wherein the polymeric polishing speed improver comprises at least one negative ion selected from a sulfonic acid ion (SO3-) and a sulfate ion (OSO3-) at a side chain of a carbon chain.

Abstract translation: 提供了用于抛光金属的浆料组合物，以提高半导体制造的效率和产率，这是由于高抛光速度和对抛光对象的低腐蚀性。 用于抛光金属的浆料组合物包括聚合物抛光速度改进剂和酸性水溶液，其中所述聚合物抛光速度改进剂包含在一侧的至少一种选自磺酸根离子（SO 3 - ）和硫酸根离子（OSO 3 - ）的负离子 链条链。

公开(公告)号：KR1020080088747A

公开(公告)日：2008-10-06

申请号：KR1020070031423

申请日：2007-03-30

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  윤보언 ,  홍창기

IPC: H01L21/304

CPC classification number: H01L22/32 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7684

Abstract: A method for detecting a defect of a CMP(chemical mechanical polishing) process is provided to grasp the state of the surface of a wafer without using expensive defect inspection equipment by examining defects like scratch of a polishing oxide layer by an electrical inspection method. An etch-stop layer(30) is formed on a wafer(10). A buffer oxide layer(20) is formed on the wafer. A predetermined thickness of a polishing oxide layer(40) is formed on the etch-stop layer. A CMP process is performed on the polishing oxide layer to form a scratch. The polishing oxide layer having the scratch is isotropically etched to increase the area of the scratch of the polishing oxide layer. The polishing oxide layer having the scratch with the increased area is removed to correspond to a predetermined combo pattern so that a trench of a predetermined depth is formed. A conductive metal layer is formed on the resultant wafer. The conductive metal layer is flatly removed to expose the polishing oxide layer so that a defect pattern and the combo pattern corresponding to the scratch exposed by the polishing oxide layer. A probe of an electrical inspecting apparatus comes in contact with both lateral pad electrodes of the combo pattern to electrically inspect whether the defect pattern crossing the combo pattern exists.

Abstract translation: 提供了一种用于检测CMP（化学机械抛光）工艺缺陷的方法，以通过电检查方法检查抛光氧化物层的缺陷等缺陷来掌握晶片表面的状态，而无需使用昂贵的缺陷检查设备。 在晶片（10）上形成蚀刻停止层（30）。 在晶片上形成缓冲氧化物层（20）。 在蚀刻停止层上形成预定厚度的抛光氧化物层（40）。 在抛光氧化物层上进行CMP工艺以形成划痕。 具有划痕的抛光氧化物层被各向同性地蚀刻以增加抛光氧化物层的划痕面积。 具有增加面积的划痕的抛光氧化物层被去除以对应于预定的组合图案，使得形成预定深度的沟槽。 在所得晶片上形成导电金属层。 导电金属层被平坦地去除以暴露抛光氧化物层，使得缺陷图案和对应于由抛光氧化物层暴露的划痕的组合图案。 电气检查装置的探针与组合图案的两个侧面焊盘电极接触以电检查是否存在与组合图案相交的缺陷图案。

公开(公告)号：KR1020080083410A

公开(公告)日：2008-09-18

申请号：KR1020070023903

申请日：2007-03-12

Applicant: 삼성전자주식회사

Inventor： 최재광 ,  김호영 ,  윤보언 ,  홍명기 ,  홍창기

IPC: H01L21/304

Abstract: An apparatus for analyzing a surface of a wafer polishing pad and a method for analyzing the surface of the wafer polishing pad using the same are provided to inspect a surface of the pad by extracting a contact rate between the pad and a plate. A flat plate(206) is loaded on an upper surface of a pad(200). A pressure unit(202) applies predetermined pressure to the flat plate unit. A plate pushing unit(204) fixes and presses an edge region of a flat plate. An optical measurement unit(208) measures a contact area between the pad and the flat plate by measuring intensity of light reflected from an interface between the pad and the flat plate. A control unit(210) compares a predetermined reference range with the contact area between the pad and the flat plate which is measured through the optical measurement unit.

Abstract translation: 提供一种用于分析晶片抛光垫的表面的装置和用于分析晶片抛光垫的表面的方法，用于通过提取焊盘和板之间的接触率来检查焊盘的表面。 平板（206）装载在垫（200）的上表面上。 压力单元（202）对平板单元施加预定的压力。 板推动单元（204）固定并按压平板的边缘区域。 光学测量单元（208）通过测量从垫和平板之间的界面反射的光的强度来测量焊盘和平板之间的接触面积。 控制单元（210）将预定的参考范围与通过光学测量单元测量的垫和平板之间的接触面积进行比较。