公开(公告)号：EP1599903A2

公开(公告)日：2005-11-30

申请号：EP04716631.9

申请日：2004-03-03

Applicant: Wavecom

Inventor： JOUAN, Jacky ,  KORDJANI, Bachir

IPC: H01L23/552 ,  H01L25/16 ,  H05K9/00

CPC classification number: H05K3/403 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/141 ,  H05K1/185 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/4644 ,  H05K2201/09436 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/4913 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a method for producing a component or a module comprising a component assembly arranged on a substrate in a housing which is mountable on a printed circuit. The inventive method consists of at least one stage when at least one part of the module is coated with an insulating material, and at least one stage when at least one conductive area is produced on one part of said insulating material in such a way that the areas forming and/or receiving at least one part of the component and/or at least one interconnection element are defined.

公开(公告)号：EP1465471A3

公开(公告)日：2005-07-27

申请号：EP04007916.2

申请日：2004-04-01

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Tomita, Yoshihiro ,  Nakamura, Tadashi ,  Ishimaru, Yukihiro ,  Sugaya, Yasuhiro ,  Honda, Kazuyoshi ,  Okazaki, Sadayuki

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/117 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4069 ,  H05K3/467 ,  H05K2201/0367 ,  H05K2201/0919 ,  H05K2201/09436 ,  H05K2201/09709 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2203/0733 ,  H01L2224/0401

Abstract: A wiring board that allows the high-density connection with a plurality of circuit boards within a limited area, a manufacturing method for the same and electronic equipment using the same are provided. A wiring board 100 includes: a plurality of conductive layers 1A to 1G each including one or more wirings for transmitting signals; and a plurality of insulation layers 2 for insulating the respective conductive layers 1A to 1G. The conductive layers 1A to 1G and the insulation layers 2 are laminated alternately, and each of the plurality of conductive layers 1A to 1G is provided with a terminal 1AT to 1GT at at least one of both ends. The terminals 1AT to 1GT are formed stepwise and separated by the insulation layers 2 in a cross-sectional shape of a lamination structure of the conductive layers 1A to 1G and the insulation layers 2.

Abstract translation: 提供允许在有限区域内与多个电路板进行高密度连接的布线板，其制造方法和使用该布线板的电子设备。 布线板100包括：多个导电层1A至1G，每个导体层包括用于传输信号的一个或多个布线; 以及用于绝缘各导电层1A至1G的多个绝缘层2。 导电层1A至1G和绝缘层2交替层叠，并且多个导电层1A至1G中的每一个在两端中的至少一个处设置有端子1AT至1GT。 端子1AT至1GT以导电层1A至1G和绝缘层2的叠层结构的横截面形状逐级形成并由绝缘层2分隔开。

公开(公告)号：EP1549119A2

公开(公告)日：2005-06-29

申请号：EP04030634.2

申请日：2004-12-23

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Yatsu, Hiroyuki ,  Suzuki, Nobuyuki

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H01L25/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/181 ,  H05K2201/09436 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2224/05599

Abstract: There is provided an electronic circuit unit capable of reliably mounting a semiconductor chip, and a method of fabricating the same. According to an electronic circuit unit of the present invention, electrodes (5) to which bumps (9) of a semiconductor chip (8) are adhered are arranged on an upper surface (1a) of a circuit board (1), and land units (7) to which chip parts (10) is soldered are arranged on a rear surface 1b of the circuit board (1), such that an insulating plate (3) which is on the rear surface (1b) of the circuit board (1) is supported by a supporting jig (11) during a mounting process of the semiconductor chip, and the circuit board (1) is not tilted. Therefore, an electronic circuit unit ensuring that the semiconductor chip is mounted with a reliable mounting capability can be obtained.

Abstract translation: 提供了能够可靠地安装半导体芯片的电子电路单元及其制造方法。 根据本发明的电子电路单元，在电路板（1）的上表面（1a）上布置有与半导体芯片（8）的凸块（9）相连的电极（5） 在电路板（1）的后表面1b上布置有焊接有芯片部件（10）的电路板（7），使得电路板（1）的背面（1b）上的绝缘板（3） ）在半导体芯片的安装处理期间由支撑夹具（11）支撑，并且电路板（1）不倾斜。 因此，可以获得确保半导体芯片安装有可靠的安装能力的电子电路单元。

公开(公告)号：EP1392089A1

公开(公告)日：2004-02-25

申请号：EP02255849.8

申请日：2002-08-21

Applicant: Ultratera Corporation

Inventor： Maa, Chong-Ren ,  Chih, Wan-Kuo ,  Tsou, Ching-Hua

IPC: H05K1/11 ,  H05K3/34 ,  H01L21/60

CPC classification number: H01L24/16 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K1/112 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2201/09981 ,  H05K2201/10674 ,  H05K2203/054 ,  H01L2224/0401

Abstract: A printed circuit board (PCB), which has bonding pads (21) thereon for mounting a flip chip, comprises a substrate (10) having a conductor pattern (20), which is composed of a plurality of traces in a specific layout. A solder mask (30) is provided on the substrate (10) sheltering the conductor pattren (20). The solder mask (30) is provided with vias (31) to expose the conductor pattern (20) at predetermined portions, and pad layers (40) are provided on the side walls of the vias (31) of the solder mask (30) respectively and are electrically connected with the conductor pattern (20) at the portions exposed via the vias (31) respectively to form the bonding pads (21) of the printed circuit board. Such that when the flip chip (70) has solder bump (71) injected into the bonding pads (21), the solder bumps (71) will be filled therein and fixedly connected with the pad layers (40) to couple the flip chip (70) with the PCB in a fixedly status.

Abstract translation: 在其上具有用于安装倒装芯片的接合焊盘（21）的印刷电路板（PCB）包括具有导体图案（20）的基板（10），其由特定布局的多个迹线组成。 在基板（10）上设置有阻挡导体板（20）的焊接掩模（30）。 焊接掩模（30）设置有通孔（31）以在预定部分露出导体图案（20），并且焊盘层（40）设置在焊接掩模（30）的通孔（31）的侧壁上， 分别在通过通孔（31）暴露的部分处与导体图案（20）电连接以形成印刷电路板的接合焊盘（21）。 使得当倒装芯片（70）具有注入到焊盘（21）中的焊料凸点（71）时，焊料凸块（71）将被填充在其中并与焊盘层（40）固定连接，以将倒装芯片（ 70），PCB处于固定状态。

公开(公告)号：EP0818946B1

公开(公告)日：2003-06-25

申请号：EP97305014.9

申请日：1997-07-08

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Matsuno, Yukio

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K1/113 ,  H05K1/095 ,  H05K3/0094 ,  H05K3/181 ,  H05K3/247 ,  H05K3/4007 ,  H05K3/429 ,  H05K3/4685 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0959 ,  H05K2203/072

公开(公告)号：EP0221924A1

公开(公告)日：1987-05-20

申请号：EP86902620.0

申请日：1986-03-31

Applicant: AMP INCORPORATED (a New Jersey corporation)

Inventor： DERY, Ronald, Allen ,  GENTRY, William, Gray ,  JONES, Warren, Charlie ,  MAY, Clifton, Carl, Jr. ,  WENTINK, Steven, George

IPC: H01B7 ,  H01R4 ,  H01R11 ,  H01R12 ,  H05K3 ,  H05K1

CPC classification number: H05K3/323 ,  H01R4/04 ,  H05K1/0393 ,  H05K1/095 ,  H05K1/148 ,  H05K1/181 ,  H05K1/189 ,  H05K3/247 ,  H05K3/28 ,  H05K3/361 ,  H05K2201/035 ,  H05K2201/09436 ,  H05K2201/10136 ,  H05K2203/066

Abstract: Assemblage de câbles plats flexibles destiné à former une connexion de faible épaisseur entre deux organes de circuit électrique, possédant chacun une rangée de tracés conducteurs faiblement écartés (18). Le câble (2) comprend une rangée de tracés (18), un film polymère isolant (20) recouvrant chaque côté de la rangée. Celle-ci est également exposée à chaque extrémité du câble cavalier, et la partie d'extrémité exposée est recouverte d'une couche d'un adhésif conducteur anisotrope (22). Le câble est conçu pour relier électriquement un panneau d'affichage plat (220) à une carte de circuit imprimé (222), le câble cavalier (210) formant la connexion entre les conducteurs (221) sur le panneau d'affichage et les conducteurs sur la carte de circuit imprimé. Est également décrit un assemblage de câbles cavaliers, comprenant des composants électriques (224) pouvant être montés en surface, qui sont connectés électriquement et fixés mécaniquement aux tracés (230) de l'assemblage de câbles cavaliers à l'aide d'un adhésif conducteur anisotrope (22). Est également décrit un assemblage de câbles conçu spécialement pour être utilisé comme dérivation.

公开(公告)号：EP0071003A1

公开(公告)日：1983-02-09

申请号：EP82104977.2

申请日：1982-06-07

Applicant: PREH, Elektrofeinmechanische Werke Jakob Preh Nachf. GmbH & Co.

Inventor： Ambros, Peter, Dipl.-Chem. ,  Müller, Walter

IPC: C23C20/04 ,  C23C18/38 ,  H05K3/12

CPC classification number: H01L21/705 ,  H05K1/095 ,  H05K1/167 ,  H05K3/184 ,  H05K3/4661 ,  H05K2201/09436 ,  H05K2201/10053 ,  H05K2203/1461

Abstract: Es wird ein Verfahren zur Herstellung von Widerstände und/oder Festkontakte von Schaltkontaktstellen enthaltenden Leiterplatten in im wesentlichen additiver Technik beschrieben. Zunächst werden die Widerstände und ggf. Festkontakte im gewünschten Layout aus einer geeigneten Widerstandspaste, vorzugsweise einer Pyropolymer-Widerstandspaste, auf das Substrat aufgedruckt, vorzugsweise im Siebdruckverfahren; sodann wird eine für nachfolgende stromlose Metallisierung sensibilisierte Haftvermittlerschicht in dem für die Leiterbahnen gewünschten Layout aufgebracht und sodann in einem weiteren Verfahrensstadium die freiliegenden Bereiche dieser Haftvermittlerschicht im chemisch arbeitenden Metallisierungsbad stromlos metallisiert, unter Erzeugung von lötbaren Leiterbahnen, welche die Widerstände und die Schaltkontakt-stellenbereiche in Anschlußbereichen überlappen.
Für die Herstellung der verschiedenen Widerstands-, elektrisch isolierenden Abdeck- bzw. Haftvermittlerschichten finden vorzugsweise Pasten Anwendung, die auf einer einheitlichen, gleichartigen Bindemittelgrundsubstanz aufgebaut sind, welche je nach der speziellen Funktion der betreffenden Schicht modifiziert wird. Soweit eine Sensibilisierung für nachfolgende stromlose Metallisierung erforderlich ist, wird dies durch Eindispergieren eines geeigneten Kstslysatorbestsndteils in die Bindemittelgrundsubstanz der zur Herstellung der betreffenden Schicht verwendeten Paste erreicht.

Abstract translation: 1.一种用于制造集成了电阻器和/或开关接触点的印刷电路板的方法，其特征在于，在添加工艺中，电阻器（R）和/或开关接触点区域（C）首先从 对于随后的无电流金属化敏感的电阻浆料（2,32）以期望的布局，随后对无电镀金属化敏化的粘附促进层（3,34）以条形导体（L）的期望布局施加到基底上， 和/或用于开关接触点（C），然后通过在化学操作的金属化浴中处理印刷电路板，粘附促进层（3,34）的暴露区域没有电流被金属化，产生带状导体 L）和/或开关接触点。

公开(公告)号：EP2360661B1

公开(公告)日：2014-01-08

申请号：EP09827400.4

申请日：2009-07-01

Applicant: Sharp Kabushiki Kaisha

Inventor： MORIWAKI, Hiroyuki

IPC: H05K3/36 ,  H05K1/02 ,  H05K1/11 ,  H05K3/32 ,  H01L23/498 ,  H01L27/02 ,  H01L27/12

CPC classification number: H05K3/361 ,  H01L23/49811 ,  H01L27/0203 ,  H01L27/12 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/14 ,  H05K1/025 ,  H05K1/113 ,  H05K3/323 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/09436 ,  H05K2201/10128 ,  H01L2924/00

公开(公告)号：EP2360661A1

公开(公告)日：2011-08-24

申请号：EP09827400.4

申请日：2009-07-01

Applicant: Sharp Kabushiki Kaisha

Inventor： MORIWAKI, Hiroyuki

IPC: G09F9/00 ,  G02F1/1345 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

CPC classification number: H05K3/361 ,  H01L23/49811 ,  H01L27/0203 ,  H01L27/12 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/14 ,  H05K1/025 ,  H05K1/113 ,  H05K3/323 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/09436 ,  H05K2201/10128 ,  H01L2924/00

Abstract: Provided is a circuit substrate that affords a narrower frame in display devices or the like, while suppressing connection faults between wirings and external connection terminals. The invention is a circuit substrate having a substrate, on top of which wiring, an insulating film and an external connection terminal are disposed in order. The circuit substrate is provided with an anisotropic conductive film, having conductive particles, on the external connection terminal; and the external connection terminal is connected to the wiring via at least one contact hole formed in the insulating film, with the length from one end to the other end, in a plan view, of a region formed with one or more contact holes that connect to a specific external connection terminal being greater than the diameter of each of the conductive particles.

Abstract translation: 提供了一种在显示装置等中提供较窄帧的电路基板，同时抑制布线和外部连接端子之间的连接故障。 本发明是具有基板的电路基板，其上布置有布线，绝缘膜和外部连接端子。 电路基板在外部连接端子上设置有具有导电粒子的各向异性导电膜; 并且所述外部连接端子经由形成在所述绝缘膜中的至少一个接触孔连接到所述布线，所述接触孔的长度从一端到另一端在平面图中形成有形成有一个或多个接触孔的区域 到特定的外部连接端子大于每个导电颗粒的直径。

公开(公告)号：EP1989930B1

公开(公告)日：2010-05-12

申请号：EP07751245.7

申请日：2007-02-22

Applicant: Edwards Lifesciences Corporation

Inventor： CURRY, Kenneth, M.

IPC: H05K1/11

CPC classification number: H05K3/247 ,  A61B5/1486 ,  A61B2562/125 ,  A61N1/05 ,  G01N27/3271 ,  H01L2924/0002 ,  H05K1/118 ,  H05K3/28 ,  H05K3/4664 ,  H05K2201/035 ,  H05K2201/09436 ,  H05K2203/0574 ,  Y10T29/4916 ,  H01L2924/00

Abstract: A method of creating an active electrode (10) that includes providing a flex circuit (100) having an electrode (120) made of a first material and providin a first mask (200) over the flex circuit, the first mask having an offset region (305) and an opening (220) that exposes the electrode. The method also includes depositing a second material (300) over the offset region and the opening, the second material being different from the first material an providing a second mask (400) over the second material, the second mask havin a opening (405) over a portion of the second material that is over the offset region.