公开(公告)号：EP0936548B1

公开(公告)日：2004-09-15

申请号：EP99300528.9

申请日：1999-01-26

Applicant: Compaq Computer Corporation

Inventor： Wisecup, George D.

IPC: G06F11/14

CPC classification number: G06F11/1433

公开(公告)号：EP0632379B1

公开(公告)日：2004-08-18

申请号：EP94108649.8

申请日：1994-06-06

Applicant: Compaq Computer Corporation

Inventor： Sicola, Stephen J. ,  Jackson, James P. ,  Oakey, Roger L. ,  Brame, Richard G. ,  Mclean, Ronald H. ,  Walker, Michael D. ,  Fava, Thomas F. ,  Adams, Thomas Gene

IPC: G06F11/16 ,  G06F11/20

CPC classification number: G06F11/2089 ,  G06F11/1008 ,  G06F11/1662 ,  G06F11/201 ,  G06F11/2097

Abstract: A fault tolerant storage controller utilizing tightly coupled dual controller modules. The controller modules each check to see if another controller module or cache module is present and, if so, then all configuration information with respect to the controller modules and attached devices are shared between them. Configuration information may be entered into either or both of the controller modules and the information is shared dynamically. Each cache module may be "locked" by an individual controller module to prevent the other controller module from inadvertently disturbing the contents of the other controller module's cache. During initialization, each controller module checks for the existence of an associated cache module and, if present, it is immediately "locked" by the controller module. Should a controller module fail or give an indication of a malfunction, the other controller module will disable or "kill" the malfunctioning controller module thereby resetting it and releasing any lock it may have had on its cache module. In those instances where the cache module is a write cache, the surviving controller module can resume operations where the malfunctioning controller module left off and complete any remaining writes to the disabled controller module's storage devices preventing the loss of any host computer data. The controller modules are tolerant of the other controller module failing and then rebooting and the sequence of events is detected and recognized by the surviving controller module such that it does not disable the one that failed. The dual controller modules communicate asynchronously to verify that they are each operational and to exchange and verify configuration information and to provide operational status dynamically.

公开(公告)号：EP0819999B1

公开(公告)日：2004-04-28

申请号：EP97305237.6

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Hallowell, William C. ,  Fritz, Brian C.

IPC: G06F1/30 ,  G06F11/14

CPC classification number: G06F9/4418 ,  G06F1/30 ,  G06F11/1441 ,  Y02D10/44

Abstract: A dynamic hibernation time apparatus monitors and ensures that battery packs in a computer system have sufficient energy capacity to sustain a proper saving of the hibernation file into the hard disk drive. The invention determines the memory size of the computer and adds the storage space needed to store the chip register contents to arrive at the determination of the hibernation file size. Next, the time necessary to save the hibernation file on the disk data storage device and the hibernation energy required to operate the disk data storage device to completely save the hibernation file are determined. When the battery capacity drops within a range of the previously computed hibernation energy, a warning message is generated at the user and the hibernation file is saved. The computer is shut down after the hibernation file has been properly saved. Thus, by determining the total memory size to be saved in the hibernation file, by determining the time and the energy required to completely store the hibernation file into the disk drive, and by sensing either the battery capacity or requesting that the smart battery sends an alarm to initiate the hibernation file saving process, the present invention ensures that sufficient energy exists in the battery packs to properly save the hibernation file onto the hard disk drive before system shut down occurs due to low battery capacity without wasting energy by determining the set point based on a maximum memory configuration.

公开(公告)号：EP0768599B1

公开(公告)日：2003-12-17

申请号：EP96307279.8

申请日：1996-10-04

Applicant: COMPAQ COMPUTER CORPORATION (a Delaware corporation)

Inventor： Schultz, Stephen M. ,  Thompson, Mark J.

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F11/1096 ,  G06F3/0626 ,  G06F3/0632 ,  G06F3/0689 ,  G11C29/74

Abstract: A system for performing on-line reconfiguration of a disk array in which a source logical volume is reconfigured to a destination logical volume. Disk array configuration is invoked if a new physical drive is inserted, or a drive is removed. Reconfiguration can also be performed if the user desires to change the configuration of a particular logical volume, such as its stripe size. The disk array reconfiguration is run as a background task by firmware on a disk controller board. The reconfigure task first moves data from the source logical volume to a posting memory such as RAM memory. The reconfigure task operates one stripe at a time, with the stripe size being that of the destination logical volume. Once a stripe of data is moved into the posting memory, it is written back to corresponding locations in the destination logical volume. The reconfigure task continues until all data in the source logical volume have been moved into the destination logical volume. While the reconfigure task is working on a particular logical volume, data remains accessible to host write and read requests.

公开(公告)号：EP0840226B1

公开(公告)日：2003-12-10

申请号：EP97308217.5

申请日：1997-10-16

Applicant: Compaq Computer Corporation

Inventor： Culley, Paul R. ,  Miller, Joseph P. ,  Hull, Daniel S. ,  Tavallaei, Siamak

IPC: G06F11/22

CPC classification number: G06F11/0745 ,  G06F11/0748 ,  G06F11/079

公开(公告)号：EP0899719B1

公开(公告)日：2003-10-15

申请号：EP98115010.5

申请日：1998-08-10

Applicant: Compaq Computer Corporation

Inventor： Glickman, Oren ,  Joerg, Christopher Frank

IPC: G10L15/28

CPC classification number: G10L15/26

公开(公告)号：EP0820021B1

公开(公告)日：2003-09-17

申请号：EP97305239.2

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Maguire, David J. ,  Riley, Dwight D. ,  Edwards, James R.

IPC: G06F13/40

CPC classification number: G06F13/4045

公开(公告)号：EP0820012B1

公开(公告)日：2003-05-07

申请号：EP97303790.6

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Autor, Jeffrey S. ,  Culley, Paul R. ,  Miller, Joseph P. ,  Tavallaei, Siamak ,  Basile, Barry S. ,  Richard, Elizabeth A. ,  Rose, Eric E.

IPC: G06F11/14

CPC classification number: G06F11/2005 ,  G06F11/0757 ,  G06F11/10 ,  G06F11/2007 ,  G06F11/2012 ,  G06F11/221 ,  G06F11/2221 ,  G06F11/349

公开(公告)号：EP0768607B1

公开(公告)日：2003-04-02

申请号：EP96307280.6

申请日：1996-10-04

Applicant: Compaq Computer Corporation

Inventor： Callison, Ryan A. ,  Chard, Gary F.

IPC: G06F11/10 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F11/1076 ,  G06F2211/1054

Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller that acts as an interface between a PCI bus and a DRAM that includes a write-posting cache portion and an XOR buffer portion. The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.

公开(公告)号：EP0851425B1

公开(公告)日：2003-03-19

申请号：EP97310690.9

申请日：1997-12-31

Applicant: Compaq Computer Corporation

Inventor： Noonan, Robert W., II

IPC: G11C7/00

CPC classification number: G11C7/1024