公开(公告)号：EP2619793A2

公开(公告)日：2013-07-31

申请号：EP11827724.3

申请日：2011-09-26

Applicant: Intel Corporation

Inventor： ZOU, Bin ,  GUO, Yan ,  SANKMAN, Robert L. ,  HE, Jiangqi

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01R43/16 ,  H01L23/49811 ,  H01L2924/0002 ,  H01R12/57 ,  H01R2103/00 ,  H05K1/0219 ,  H05K1/0231 ,  H05K1/0242 ,  H05K1/0251 ,  H05K1/113 ,  H05K2201/09336 ,  H05K2201/09663 ,  H05K2201/1031 ,  Y02P70/611 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Methods and apparatus relating to self-referencing pins are described. In one embodiment, a pin electrically couples a first agent to a second agent. The pin includes two or more portions that are at least partially separated by an insulator, e.g., to improve crosstalk performance. Other embodiments are also disclosed and claimed.

公开(公告)号：EP1959716A3

公开(公告)日：2009-10-21

申请号：EP08100555.5

申请日：2008-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Park, Hark Byeong ,  Seol, Byong Su ,  Kim, Hyung Geun ,  Park, Hyun Ho ,  Lee, Jong Sung ,  Lee, Hyung Seok ,  Moon, Young Jun

IPC: H05K1/02

CPC classification number: H05K1/0234 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/09309 ,  H05K2201/09336

Abstract: Disclosed is a multilayer printed circuit board (10). The multilayer printed circuit board (10) includes a power source surface (12) to provide power to each component disposed on the power source surface, a ground surface (13) having a reference voltage, a strip line (14) which passes through the power source surface and/or the ground surface so as to transmit signals between components, an antenna installed in proximity to a sectional region of the power source surface and the ground surface, and an electromagnetic wave reduction member (20) which is provided between the power source surface (12) and the ground surface (13) to effectively reduce an electromagnetic wave generated from the strip line (14).

Abstract translation: 公开了一种多层印刷电路板（10）。 多层印刷电路板（10）包括：电源表面（12），用于向设置在电源表面上的每个部件供电;具有参考电压的接地表面（13）;带状线（14），其穿过 电源表面和/或接地表面，以便在部件之间传输信号，天线安装在电源表面的截面区域和接地表面附近，以及电磁波减少部件（20），其设置在电源表面和/ 电源表面（12）和接地表面（13），以有效地减少从带状线（14）产生的电磁波。

公开(公告)号：EP2109349A1

公开(公告)日：2009-10-14

申请号：EP08103866.3

申请日：2008-05-08

Applicant: Mediatek Inc.

Inventor： Chen, Nan-Jang ,  Lin, Hong-Chin

IPC: H05K1/02 ,  H01L23/66 ,  H05K3/46

CPC classification number: H05K1/0216 ,  H01L2924/0002 ,  H05K3/222 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/10363 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A printed circuit board (500a-d) is disclosed. The printed circuit board comprises a substrate (200) having a top surface (202) and a bottom surface (203). A ground plane (228) is on the bottom surface. A first signal trace (212a) is on the top surface along a first direction. At least two isolated power planes (208, 210) are on the top surface adjacent to opposite sides of the first signal trace, respectively. A conductive connection (216) along a second direction couples to the two power planes, across the first signal trace (212a) without electrically connecting to the signal trace, wherein the first signal trace (212a) doesn't directly pass over any split of the ground plane (228).

Abstract translation: 公开了一种印刷电路板（500a-d）。 印刷电路板包括具有顶表面（202）和底表面（203）的基底（200）。 接地平面（228）位于底面。 第一信号迹线（212a）沿着第一方向在顶表面上。 至少两个隔离电源平面（208,210）分别位于与第一信号迹线的相对侧相邻的顶表面上。 沿着第二方向的导电连接（216）跨过第一信号迹线（212a）耦合到两个电源层，而不电连接到信号迹线，其中第一信号迹线（212a）不直接通过 地面（228）。

公开(公告)号：EP1414279A3

公开(公告)日：2006-10-25

申请号：EP03022912.4

申请日：2003-10-09

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Furutani, Koji, (170)Intellectual Property Dept.

IPC: H05K1/02 ,  H05K3/46 ,  H01L23/538

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L2924/0002 ,  H04B1/005 ,  H04B1/0057 ,  H04B1/006 ,  H04B1/52 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/0979 ,  H01L2924/00

Abstract: In a high-frequency module, intermediate ground electrodes (Go1, Gm1, Gg1, Go2, Gm2, Gg2) are provided between a common ground electrode (Gd) and upper-surface ground electrodes (Gq1, Gq2,) for mounting high-frequency components (21, 22) on an upper surface of a multilayer substrate. With regard to the number of via-hole conductors interconnecting ground electrodes, the number of via-hole conductors (Vdg) between the intermediate ground electrodes (Go1, Gm1, Gg1, Go2, Gm2, Gg2) and the common ground electrode (Gg) is larger than the number of via-hole conductors (Voq) between the upper-surface ground electrodes (Gq1, Gq2) and the intermediate ground electrodes (Go1, Gm1, Gg1, Go2, Gm2, Gg2).

Abstract translation: 多层基板（1）通过层压电极层和电介质层（11-15）而形成。 高频部件（21,22）的接地端子与基板的上表面接地电极（Gq1，Gq2）连接。 使用通孔导体（Vdg，Vmo，Voq，Vgm），将接地电极（Go1，Gm1，Gg1，Go2，Gm2，Gg2）设置在接地电极（Gd）和上表面接地电极之间。 通信设备还包括独立的权利要求。

公开(公告)号：EP1061784B1

公开(公告)日：2006-09-27

申请号：EP98958417.2

申请日：1998-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： ROG, Andrei Leonidovich ,  KORULIN, Vitaly Nikolaevich ,  OSIPOV, Oleg Dmitrievich ,  SOLDATENKOV, Anatoly Nikolaevich ,  USTINOV, Igor Vladimirovich ,  MALASHIN, Viktor Ivanovich

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/14 ,  H01L27/02

CPC classification number: H05K1/0218 ,  H05K1/0237 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09354 ,  H05K2201/09618 ,  H05K2201/09663 ,  H05K2201/09972

Abstract: The present invention pertains to the field of radio-electronics and may be used in the structures of radio-electronic units for receiving and processing signals from satellite radio-navigation systems. This invention essentially relates to a radio-electronic unit that comprises a multi-layered printed plate as well as a plurality of conductors. These conductors, which are used for shielding the corresponding signal communication conductor and which are arranged on both sides thereof, are connected to ground planes through the metallised openings of inter-layer connections formed at least at the beginning and at the end of each isolation conductor so as to define a closed-loop electric circuit.

公开(公告)号：EP1098555A3

公开(公告)日：2005-04-13

申请号：EP00309666.6

申请日：2000-11-01

Applicant: CANON KABUSHIKI KAISHA

Inventor： Otaki, Toru ,  Inagawa, Hideho ,  Osaka, Toru

IPC: H05K1/11

CPC classification number: H05K1/112 ,  H05K2201/09227 ,  H05K2201/09336 ,  H05K2201/0939 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A printed wiring board having assembled thereon a grid array type package, a multi-terminal device with many terminals arranged in matrix, is provided, through first signal connection holes, signal lines, and second connection holes, with many numbers of lands divided into plural blocks, being arranged in matrix on a first layer to connect each terminal of the multi-terminal device correspondingly, signal line patterns connected with many lands, and drawn out in the same direction per block, and first signal patterns from lands positioned on the innermost line of many lands. Then, the wiring patterns of the signal lines are drawn out regularly from many lands formed in matrix on the assembling surface of the grid array type package to make it easier for the printed wiring board to effectuate wiring connections without making them complicated or increasing the number of layers of the printed wiring board. Also, with the provision of ground patterns that surround signal lines, it is made possible to reduce unwanted radiation, as well as to suppress the occurrence of malfunctions of electronic equipment due to reflections and ground bounces.

公开(公告)号：EP1405531A2

公开(公告)日：2004-04-07

申请号：EP02742264.1

申请日：2002-06-24

Applicant: ADC Telecommunications, Inc.

Inventor： SCHMOKEL, Paul, W.

IPC: H04Q1/10 ,  H05K7/00 ,  H04M11/06

CPC classification number: H05K1/0216 ,  H04Q1/06 ,  H04Q1/14 ,  H04Q2201/10 ,  H04Q2201/12 ,  H04Q2201/14 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09336

Abstract: A telecommunications device including a plurality of splitter cards (55) mounted in a chassis (52). The device also includes a circuit board (68) and plurality of card edge connectors (96) for providing electrical connections between the splitter cards and the circuit board. The device further includes POTS connectors, LINE connectors and DATA connectors. The circuit board includes a first layer having first tracings that electrically connect contacts of at least one of the POTS, LINE or DATA connectors to at least one of the card edge connectors; a second layer having second tracings that electrically connect contacts of at least one of the POTS, LINE or DATA connectors to at least one of the card edge connectors; and a third layer having third tracings that electrically connect contacts of at least one of the POTS, LINE or DATA connectors to at least one of the card edge connectors. The second layer is positioned between the first and third layers. A majority of the second layer is covered by a grounding plane. The grounding plane and the second tracings are co-planar such that the grounding plane adds no additional thickness to the second layer. The grounding plane is positioned between the first and third tracings to reduce cross-talk between the first and third tracings.

公开(公告)号：EP1098555A2

公开(公告)日：2001-05-09

申请号：EP00309666.6

申请日：2000-11-01

Applicant: CANON KABUSHIKI KAISHA

Inventor： Otaki, Toru ,  Inagawa, Hideho ,  Osaka, Toru

IPC: H05K1/11

CPC classification number: H05K1/112 ,  H05K2201/09227 ,  H05K2201/09336 ,  H05K2201/0939 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A printed wiring board having assembled thereon a grid array type package, a multi-terminal device with many terminals arranged in matrix, is provided, through first signal connection holes, signal lines, and second connection holes, with many numbers of lands divided into plural blocks, being arranged in matrix on a first layer to connect each terminal of the multi-terminal device correspondingly, signal line patterns connected with many lands, and drawn out in the same direction per block, and first signal patterns from lands positioned on the innermost line of many lands. Then, the wiring patterns of the signal lines are drawn out regularly from many lands formed in matrix on the assembling surface of the grid array type package to make it easier for the printed wiring board to effectuate wiring connections without making them complicated or increasing the number of layers of the printed wiring board. Also, with the provision of ground patterns that surround signal lines, it is made possible to reduce unwanted radiation, as well as to suppress the occurrence of malfunctions of electronic equipment due to reflections and ground bounces.

Abstract translation: 通过第一信号连接孔，信号线和第二连接孔，设置有多个阵列型封装的印刷电路板，具有多个端子排列成矩阵状的多端子装置，其中多个焊盘分成多个 块，以矩阵形式布置在第一层上，以相应地连接多终端设备的每个终端，与许多焊盘相连并沿与每块相同的方向拉出的信号线图案，以及位于最内层的焊盘的第一信号图案 许多土地线。 然后，信号线的布线图形从格栅阵列型封装的组装表面上的矩阵形状的多个区域中规则地拉出，使得印刷布线板更容易实现布线连接而不使其复杂或增加数量 的印刷线路板的层。 此外，通过提供环绕信号线的接地图案，可以减少不需要的辐射，并且抑制由于反射和地面反弹而导致的电子设备故障的发生。

公开(公告)号：EP0766503A3

公开(公告)日：1999-03-31

申请号：EP96115548.8

申请日：1996-09-27

Applicant: CANON KABUSHIKI KAISHA

Inventor： Ohtaki, Toru, c/o Canon K.K. ,  Ichida, Yasuteru, c/o Canon K.K. ,  Takeuchi, Yasushi, c/o Canon K.K.

IPC: H05K1/02 ,  H05K1/16

CPC classification number: H01L23/48 ,  H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/0298 ,  H05K1/162 ,  H05K1/165 ,  H05K3/3421 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/1006 ,  H05K2201/10689 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In a multi-layered printed circuit board on which an LSI having a plurality of power supply pins and a plurality of signal pins is mounted, and a grid array package which adopts the printed circuit board, some or all of the plurality of power supply pins are connected to a power supply pattern via an inductance pattern, thereby reducing generation of radiation noise.

Abstract translation: 在其上安装有多个电源引脚和多个信号引脚的LSI的多层印刷电路板和采用该印刷电路板的栅格阵列封装中，多个电源引脚中的一些或全部 通过电感图案连接到电源图案，从而减少辐射噪声的产生。

公开(公告)号：WO2016048584A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/047639

申请日：2015-08-31

Applicant: TYCO ELECTRONICS CORPORATION

Inventor： BEHZIZ, Arash ,  COSTELLO, Brian Patrick ,  HERRING, Michael David

IPC: H01R13/6595 ,  H01R12/59 ,  H05K1/14

CPC classification number: H01R12/716 ,  H01R12/594 ,  H01R12/62 ,  H01R13/6588 ,  H01R13/6594 ,  H01R13/6595 ,  H05K1/0219 ,  H05K1/111 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/09336 ,  H05K2201/09709 ,  H05K2201/10356 ,  H05K2201/10371

Abstract: A cable assembly comprises a carrier board (150) having a terminating side (162) and a mounting side (164) that face in opposite directions. The terminating side includes a contact array (170) of electrical contacts (201), and the mounting side (164) includes a mating array (260) of electrical contacts (261). The contact array (170) and the mating array (260) are interconnected to each other through conductive pathways of the carrier board. The contact array (170) along the terminating side overlaps with the mating array (260) along the mounting side. The carrier board is configured to be mounted onto an electrical component having a two-dimensional array (138) of electrical contacts such that the mating array (260) electrically engages the two-dimensional array. The cable assembly includes a plurality of cables (126, 127, 128) having cable end portions (130) including exposed signal conductors (174) that are terminated to corresponding electrical contacts (201) of the contact array (170).

Abstract translation: 电缆组件包括具有终止侧（162）和面向相反方向的安装侧（164）的承载板（150）。 端接侧包括电触点（201）的接触阵列（170），并且安装侧（164）包括电触点（261）的匹配阵列（260）。 接触阵列（170）和配合阵列（260）通过载体板的导电路径彼此互连。 沿着终端侧的接触阵列（170）沿着安装侧与配合阵列（260）重叠。 载体板被配置为安装在具有电接触的二维阵列（138）的电气部件上，使得配合阵列（260）电二维阵列电接合。 电缆组件包括具有电缆末端部分（130）的多个电缆（126,127,128），电缆端部分包括暴露的信号导体（174），其终止于接触阵列（170）的相应的电触点（201）。