公开(公告)号：EP2294618A1

公开(公告)日：2011-03-16

申请号：EP09757233.3

申请日：2009-05-29

Applicant: PolyIC GmbH & Co. KG

Inventor： KNOBLOCH, Alexander ,  FIX, Walter

IPC: H01L27/28 ,  H01L51/00

CPC classification number: H01L27/283 ,  H01L51/0018 ,  H05K1/0393 ,  H05K1/16 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/09763 ,  H05K2201/09909

Abstract: The invention relates to an electronic circuit (1, 10, 100, 101, 102) comprising at least two organic components (I, II, III, IV, V) connected to each other by means of circuit paths, said components having a mutual carrier substrate (2). The components (I, II, III, IV, V) and the circuit paths are formed from layer positions (3a, 3b, 3c, 3d). An upper layer position (3d') of the electronic circuit (1, 10, 100, 101, 102) facing away from the carrier substrate (2) is configured from an electrically conducting material in the manner of a pattern. The pattern-shaped upper layer position (3d') is equipped with at least one protective layer (4a, 4b, 4c, 4d) that is congruent to the upper most layer position (3d') on the side thereof facing away from the carrier substrate (2). The at least two organic components (I, II, III, IV, V) comprise at least one first component (I, II) of a first component type, and at least one second component (III, IV, V) of a second component type differing thereto. Components (I, II) of the same component type are protected by a protective layer (4a) of the same composition and/or the same construction.

Abstract translation: 本发明涉及包括通过电路路径彼此连接的至少两个有机部件（I，II，III，IV，V）的电子电路（1,10,100,101,102），所述部件具有互相 载体基板（2）。 元件（I，II，III，IV，V）和电路路径由层位置（3a，3b，3c，3d）形成。 背离载体衬底（2）的电子电路（1,10,100,101,102）的上层位置（3d'）由导电材料以图案的方式配置。 图案形状的上层位置（3d'）配备有至少一个保护层（4a，4b，4c，4d），所述保护层在其背向载体的一侧上与最上层位置（3d'）一致 衬底（2）。 所述至少两种有机组分（I，II，III，IV，V）包含第一组分类型的至少一种第一组分（I，II）和至少一种第二组分 组件类型不同。 相同部件类型的部件（I，II）由相同组成和/或相同结构的保护层（4a）保护。

公开(公告)号：EP1777745A3

公开(公告)日：2010-05-05

申请号：EP06019654.0

申请日：2006-09-20

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Borland, William J. ,  Ferguson, Saul

IPC: H05K1/16 ,  H01L23/50 ,  H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09763 ,  H05K2201/10734

Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor (240) wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device (201) can be directly connected to at least one first and at least one second electrode, respectively.

公开(公告)号：EP2022832A3

公开(公告)日：2009-10-07

申请号：EP08252447.1

申请日：2008-07-17

Applicant: E. I. Du Pont de Nemours and Company

Inventor： Summers, John D. ,  Dueber, Thomas Eugene

IPC: C09D177/00 ,  C08G73/00 ,  C08G73/22 ,  H01B3/00 ,  H01L21/00 ,  H01L51/00 ,  H05K1/00 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/162 ,  C08G69/00 ,  C08G73/22 ,  H01L51/5253 ,  H05K3/1291 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.

公开(公告)号：EP1777746A3

公开(公告)日：2009-08-19

申请号：EP06020934.3

申请日：2006-10-05

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Swaminathan, Madhavan ,  Muthana, Prathap ,  Engin, Ege ,  Srinivasan, Krishna

IPC: H01L23/66 ,  H01L23/50

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/3011 ,  H05K1/162 ,  H05K2201/09763 ,  H05K2201/10674 ,  Y10S257/924

Abstract: One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.

公开(公告)号：EP2027184A2

公开(公告)日：2009-02-25

申请号：EP07796113.4

申请日：2007-06-13

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： DUEBER, Thomas, E. ,  SUMMERS, John, D.

IPC: C08G73/00 ,  C08G73/10 ,  C08J5/18 ,  C09D179/08

CPC classification number: C08G73/1039 ,  C08G73/1064 ,  C09D179/08 ,  H01G4/224 ,  H01G9/08 ,  H05K1/162 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763

Abstract: Disclosed area compositions comprising: a polyimide resin with a water absorption of 2% or less and, optionally, one or more of an electrically insulated filler, a defoamer and a colorant and one or more organic solvents. The compositions are useful as encapsulants and have a consolidation temperature of 190°C or less.

公开(公告)号：EP2022832A2

公开(公告)日：2009-02-11

申请号：EP08252447.1

申请日：2008-07-17

Applicant: E. I. Du Pont de Nemours and Company

Inventor： Summers, John D. ,  Dueber, Thomas Eugene

IPC: C09D177/00

CPC classification number: H05K1/162 ,  C08G69/00 ,  C08G73/22 ,  H01L51/5253 ,  H05K3/1291 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.

Abstract translation: 本发明涉及组合物，以及这种组合物用于保护涂层，特别是电子器件的用途。 本发明涉及涂覆有复合密封剂并嵌入印刷线路板中的箔上烧制陶瓷电容器。

公开(公告)号：EP1887622A2

公开(公告)日：2008-02-13

申请号：EP07114115.4

申请日：2007-08-09

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Mashino, Naohiro

IPC: H01L23/50

CPC classification number: H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01G4/38 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/642 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/162 ,  H05K3/007 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/435

Abstract: A capacitor built-in substrate of the present invention includes; a base resin layer (50); a plurality of capacitors (C) arranged side by side in a lateral direction in a state that the capacitors (C) are passed through the base resin layer (50), each of the capacitors (C) constructed by a first electrode (20) provided to pass through the base resin layer (50) and having projection portions (54, 56) projected from both surface sides of the base resin layer (50) respectively such that the projection portion (54) on one surface side of the base resin layer (50) serves as a connection portion (21), a dielectric layer (22) for covering the projection portion (56) of the first electrode (20) on other surface side of the base resin layer (50), and a second electrode (24) for covering the dielectric layer (22); a through electrode (T) provided to pass through the base resin layer (50) and having projection portions (54, 56a) projected from both surface sides of the base resin layer (50) respectively; and a built-up wiring (72, 72a) formed on the other surface side of the base resin layer (50) and connected to the second electrodes (24) of the capacitors (C) and one end side of the through electrode (T).

Abstract translation: 本发明的电容器内置基板包括： 基础树脂层（50）; 在电容器（C）通过基础树脂层（50）的状态下，沿横向并排布置的多个电容器（C），由第一电极（20）构成的每个电容器（C） 被设置为穿过所述基础树脂层（50）并且具有分别从所述基础树脂层（50）的两个表面侧突出的突出部（54,56），使得所述基础树脂的一个表面侧上的突出部（54） 层（50）用作连接部分（21），用于在基底树脂层（50）的另一表面侧覆盖第一电极（20）的突起部分（56）的电介质层（22） 用于覆盖介电层（22）的电极（24）; 设置用于穿过基底树脂层（50）并具有分别从基底树脂层（50）的两个表面侧突出的突出部分（54,56a）的通孔（T） 以及形成在基础树脂层（50）的另一个表面侧并与电容器（C）的第二电极（24）连通并且与通孔电极（T）的一个端部侧连接的积层布线（72,72a） ）。

公开(公告)号：EP1777744A2

公开(公告)日：2007-04-25

申请号：EP06019852.0

申请日：2006-09-22

Applicant: E.I. du Pont de Nemours and Company

Inventor： Swaminathan, Madhavan ,  Wan, Lixi ,  Engin, Ege ,  Muthana, Prathap

IPC: H01L23/498 ,  H05K1/16 ,  H01L23/50 ,  H01L23/64

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/904 ,  Y10S257/924 ,  H01L2924/00

Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising installing in said package an array of embedded discrete ceramic capacitors (1600), and optionally planar capacitor layers (1500). A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising using an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.

Abstract translation: 本发明的一个实施例提供了一种用于在1兆赫至3千兆赫，包括在所述封装安装到嵌入离散的陶瓷电容器（1600）的阵列的中间频率范围在IC提供低噪声电源包，以及任选地 平面电容器层（1500）。 另一实施例提供了一种用于在1兆赫至3千兆赫使用具有不同谐振频率的嵌入离散的陶瓷电容器，在寻求一种方式布置的阵列，其包括中间频率范围在IC提供低噪声电源包做了 电容器阵列的阻抗与在等于或低于目标阻抗值的临界中频范围的产率的阻抗值频率曲线。

公开(公告)号：EP1455558A3

公开(公告)日：2007-03-21

申请号：EP04005340.7

申请日：2004-03-05

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Borland, William ,  McGregor, David R. ,  Ferguson, Saul

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  Y10T29/435 ,  Y10T29/49155

Abstract: In a printed wiring board, a plurality of stacked innerlayer panels 100, 200, 300 have capacitors 105, 205, 305 connected in parallel by connecting a first electrode 110 of a first panel with a first electrode 210 of a second panel, and similarly connecting second electrodes 120, 220 of the first and second panels. The innerlayer panel having capacitors connected in parallel provides a high capacitance in a small x-y area. An alternative printed wiring board has a capacitor having a first foil electrode 101, and second and third electrodes located on opposite sides of the first foil electrode. Yet another printed wiring board has capacitors formed as an array of discrete foil electrodes spaced from an array of discrete printed electrodes. Forming discrete interconnected electrodes allows the electrodes to be fired without excessive thermal coefficient of expansion stresses damaging the electrodes.

公开(公告)号：EP1696716A1

公开(公告)日：2006-08-30

申请号：EP04801674.5

申请日：2004-12-06

Applicant: IBIDEN CO., LTD.

Inventor： KARIYA, Takashi ,  MOCHIDA, Akira

IPC: H05K3/46

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷线路板10包括：安装部分60，其上表面上安装有与布线图案32等电连接的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40以及夹持高介电常数层43的第一和第二层电极41和42.第一和第二层电极41和42之一连接到 半导体元件的电源线以及第一和第二层电极41和42中的任一个的另一个连接到地线。 在该多层印刷线路板10中，连接在电源线和接地线之间的层状电容器部分40中包含的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也表现出适当的去耦合效果。