公开(公告)号：JP2001147858A

公开(公告)日：2001-05-29

申请号：JP2000301559

申请日：2000-10-02

Applicant: ST MICROELECTRONICS INC

Inventor： D SHIMIZU ,  ANDREW JONES

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To efficiently perform access to a common in a cache memory system. SOLUTION: A computer system is provided with a memory system, and at least one part of the memory systems is designated as a common memory. A bus mechanism connected with the memory system with a transaction as a base is provided with a cache coherency transaction defined in the transaction set. A processor having a cache memory is connected through the bus mechanism with the transaction as a base with the memory system. A system component connected with the bus mechanism is provided with a logic for specifying a cache coherence policy. Then, the cache transaction is started according to the cache policy on the bus mechanism specified by the logic in the system component. The logic in the processor responds to the cache transaction started by executing the cache operation specified by the cache transaction.

公开(公告)号：JP2001147831A

公开(公告)日：2001-05-29

申请号：JP2000299928

申请日：2000-09-29

Applicant: ST MICROELECTRONICS INC

Inventor： EDWARDS DAVID ALAN ,  GEARTY MARGARET ROSE ,  FARRALL GLENN A ,  HASEGAWA ATSUSHI ,  RICH ANTHONY WILLIS

IPC: G06F11/28 ,  G06F11/22 ,  G06F11/26 ,  G06F11/36 ,  G06F15/78

Abstract: PROBLEM TO BE SOLVED: To provide an improved interface for transferring debug information. SOLUTION: A microcomputer having a processor and a debug circuit is provided with an exclusive link for transferring information between the processor and the debug circuit for supporting a debug operation. The processor supplies program counter information, and the program counter information is stored in the memory map type register of the debug circuit. The program counter information may be obtained as the value of a processor program counter positioned at the write back stage of a processor pipe line. Also, trace information including message information is transferred through the exclusive link in a non-intrusive mode. This microcomputer may be constituted as a single integrated circuit.

公开(公告)号：JP2001144622A

公开(公告)日：2001-05-25

申请号：JP2000298174

申请日：2000-09-29

Applicant: ST MICROELECTRONICS INC

Inventor： REZZI FRANCESCO ,  MARROW MARCUS

IPC: G11B20/14 ,  G11B20/18 ,  H03M7/14 ,  H03M13/09

Abstract: PROBLEM TO BE SOLVED: To provide an enhanced technology to encode data stored on a magnetic medium such as a computer disk. SOLUTION: A code word of this invention has data bits of a 1st group and code bits denoting data bits of a 2nd group. The codes of this invention having the code word bike this can be processed at a high efficiency and causes less error propagation, being different from conventional codes.

公开(公告)号：JP2000341934A

公开(公告)日：2000-12-08

申请号：JP2000144365

申请日：2000-05-17

Applicant: ST MICROELECTRONICS INC

Inventor： WENZEL EDWARD P

IPC: H02M3/28 ,  H02M1/10 ,  H02M3/335

Abstract: PROBLEM TO BE SOLVED: To obtain an AD and DC input power supply in which separation and operation can be carried out from both full range input AC voltage and low DC input voltage by providing an AC power supply circuit with an AC input, a rectifier circuit, a separation output transformer, and the like, and providing a DC power supply circuit with a DC input terminal connectable selectively among low voltage winding sections. SOLUTION: An AC power supply circuit 10 is provided with an AC input connector 12, an input fuse 14, an output transformer T1, and the like. A rectifier circuit 30 is also provided and connected through the fuse 14 with the AC input connector 12. The low voltage winding section 36 of the transformer T1 is connected with a DC voltage input lower than the range of a DC voltage produced by rectifying the AC input voltage. A DC power supply circuit has an input terminal formed as a connector 44 and connected with a fuse 48. Furthermore, a diode 50 is connected with the connector 44 and a switch 42 is connected with the diode 50. According to the circuitry, the DC input terminal can be connected selectively with the first primary winding terminal 18a when a nominal DC voltage is inputted to the connector 44.

公开(公告)号：JP2000243081A

公开(公告)日：2000-09-08

申请号：JP2000043897

申请日：2000-02-22

Applicant: ST MICROELECTRONICS INC

Inventor： GURITZ ELMER HENRY

IPC: G11C11/407 ,  G05F1/46 ,  G05F3/24 ,  G11C7/14 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4099 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide reference voltage having high immunity for a noise by providing a voltage divider which is connected to a voltage supply source, decides reference voltage, and supplies a voltage output signal under control of a feedback control signal, and a feedback buffer amplifier for supplying a feedback control signal to a voltage divider. SOLUTION: A feedback buffer amplifier is provided in a reference voltage generator, and a N-type transistor M0 and a P-type transistor M1 which are connected in series between VDD and ground are provided. Gates of the transistors M0. M1 are connected respectively to a N-drive output signal 36 and a P-drive output signal 38, also, the transistors M0 and M1 are connected by a node D, the node D is connected to a substrate of the transistor M1, and supplies a feedback control signal 34 to a delay element. In order to secure quick response, the transistors M0, M1 has small size, and the node D is subjected to light load.

公开(公告)号：JP2000200241A

公开(公告)日：2000-07-18

申请号：JP27916899

申请日：1999-09-30

Applicant: ST MICROELECTRONICS INC

Inventor： CHRISTIAN D CASPER

IPC: G06F13/12 ,  G06F5/06 ,  G06F13/00 ,  G06F13/38 ,  H04L12/56

Abstract: PROBLEM TO BE SOLVED: To constitute a data structure by using a descriptor link in a network device by constructing a descriptor which points a frame data buffer in a common memory and storing the descriptor. SOLUTION: Four network controllers 40 are connected to a 32-bit system bus connected to a host system 43. A host microprocessor 44 is connected to the system bus 42 as well as a common memory subsystem 46. In this case, the network device itself serves to constitute a buffer structure for, e.g. the frame data buffer, a relative descriptor link, and a descriptor. The network device constructs a transmission and/or reception descriptor link in a memory used externally in common to the host system. The network device constructs one ore more descriptors, each of which points the frame data buffer in the common memory. Then, the descriptors are stored.

公开(公告)号：JP2000196025A

公开(公告)日：2000-07-14

申请号：JP36067199

申请日：1999-12-20

Applicant: ST MICROELECTRONICS INC

Inventor： ARNAUD EVE LUPERT ,  DANIEL A THOMAS ,  ANTONIO DOOBENTO-BIEIRA

IPC: H01L27/04 ,  A61B5/117 ,  G01B7/28 ,  G01B7/34 ,  G06K9/00 ,  G06T1/00 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To realize an integrated circuit, equipped with a contact between a pad and conductive layers for making electrostatic charges escape in a sensor, and a method for forming the contact. SOLUTION: A pad 38 and composite insulating layers 16 are formed between and on conductive plates on a substrate. The insulating layers 16 can separate the conductive plates and the pad 38 and protect them from damages, and the insulating layers 16 are provided with dielectric regions which are present at the lower side of a conductive layer. Passivation layers 32 are formed on at least one part of the insulating layers 16, and a photoresist is pattern-formed on at least one part of the passivation layers 32. An opening 36 is etching- formed so as to be put through the passivation layers 32 and the insulating layers 16, and the photoresist and the conductive layer are used as a mask, in this case. Then, conductive materials are adhered in the opening 36, and an electric contact between the pad 38 and the conductive layer is formed.

公开(公告)号：JP2000188000A

公开(公告)日：2000-07-04

申请号：JP35617999

申请日：1999-12-15

Applicant: ST MICROELECTRONICS INC

Inventor： TAYLOR RONALD T

IPC: G11C11/401 ,  G11C29/06 ,  G11C29/50 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To enable a stress test at a low voltage against the oxide film of a memory cell condenser by separating a sense amplifier from a bit line, initializing all nodes that are connected to the memory cell in the test control circuit, and disabling a word line booster circuit. SOLUTION: Plural pieces of memory are provided in which a first set of alternate word lines 18a and 18c connects a memory cell 40 to half bit lines b t 110 and a second set of alternate word line 18b and 18d connects the memory cell 40 to half bit lines b c 112. With each sense amplifier of DRAM put in a separation state, and with each pre-charge voltage and half bit line grounded, each word line booster circuit is disabled or a voltage level on the word line is maintained at a low level. Since the memory cell condenser of the memory cell 40 is separated from the sense amplifier, it enables the stress test on the memory cell condenser to be carried out at a low word line voltage level independently.

公开(公告)号：JP2000187991A

公开(公告)日：2000-07-04

申请号：JP35643599

申请日：1999-12-15

Applicant: ST MICROELECTRONICS INC

Inventor： CHAN TSIU CHIU ,  NGUYEN THI N

IPC: G11C17/00 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To enable data storage inside a non-volatile associative storage device by making a storage device operable to connect a bit line to an output terminal if the first data bit has first logical level, and making the device operable to connect a complementary bit line to an output terminal if the first data bit has second logical state. SOLUTION: If the first input/output 13 is connected to the ground through a floating gate transistor 12, a CAM cell 10 is such that a transistor 28 connects a complementary bit line 30 to a transistor 32. The logic 'o' of the first input/ output 13 is applied to the gate of the transistors 26, 28, turning off the transistor 26, and connecting the complementary bit line 30 to the gate of the transistor 32. In the case where the data bit to be applied to the bit line 20 matches the data value to be stored in the transistor 12, the data bit to the complementary bit line turns on the transistor 32 and grounds a match line 34.

公开(公告)号：JP2000105699A

公开(公告)日：2000-04-11

申请号：JP24550499

申请日：1999-08-31

Applicant: ST MICROELECTRONICS INC

Inventor： NARESH H SONI

IPC: G06F9/38 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To improve the parallelism in data processing, to decrease the time for waiting the execution of instruction and to accelerate the processing speed. SOLUTION: A data processing system having distributed reservation stations 50-53 is provided and this distributed reservation stations 50-53 store the basic blocks of codes in the format of a microprocessor instruction. Accordingly, the basic block of the code can be distributed to several distributed reservation stations 50-53. Thus, the number of entries in each of distributed reservation stations 50-53 can be decreased, the duration for executing the instruction is reduced and the processing speed is accelerated.