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    Semiconductor buffer structure and semiconductor element including the same, and manufacturing method of the same
    143.
    发明专利
    Semiconductor buffer structure and semiconductor element including the same, and manufacturing method of the same 审中-公开
    半导体缓冲器结构和半导体元件及其制造方法

    公开(公告)号：JP2014053611A

    公开(公告)日：2014-03-20

    申请号：JP2013183198

    申请日：2013-09-04

    Applicant: Samsung Electronics Co Ltd ,  三星電子株式会社Samsung Electronics Co.,Ltd.

    Inventor： KIM JUN-YOUN ,  KIM JOO-SUNG ,  LIANG MOON CHENG

    IPC: H01L21/205

    CPC classification number: H05K1/0201 ,  H05K1/09 ,  H05K3/0035 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0341

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor buffer structure which reduces a dislocation density in a nitride thin film when the nitride thin film grows on a silicon substrate.SOLUTION: A semiconductor buffer structure according to the present embodiment comprises: a plurality of nitride semiconductor layers in which average relative proportions of gallium increases with distance in one direction; and a dislocation control layer formed from AlInGaN (0≤a1≤1, 0≤b1≤1, a1+b1≠1) arranged between adjacent nitride semiconductor layers among the plurality of nitride semiconductor layers. Because of interposition of the dislocation control layer, a location density of the whole of the plurality of nitride semiconductor layers can be decreased.

    Abstract translation: 要解决的问题：提供当氮化物薄膜在硅衬底上生长时减少氮化物薄膜中的位错密度的半导体缓冲结构。解决方案：根据本实施例的半导体缓冲结构包括：多个氮化物半导体 其中镓的平均相对比例随着一个方向上的距离而增加的层; 以及由位于所述多个氮化物半导体层的相邻的氮化物半导体层之间的AlInGaN（0≤a1≤1,0≤b1≤1，a1 + b1≠1）形成的位错控制层。 由于插入位错控制层，可以减少多个氮化物半导体层整体的位置密度。

    Wiring board and manufacturing method of the same
    145.
    发明专利
    Wiring board and manufacturing method of the same 有权
    接线板及其制造方法

    公开(公告)号：JP2012129368A

    公开(公告)日：2012-07-05

    申请号：JP2010279706

    申请日：2010-12-15

    Applicant: Ngk Spark Plug Co Ltd ,  日本特殊陶業株式会社

    Inventor： YAMADA ERINA ,  HIGO ICHIEI ,  SATO HIRONORI

    IPC: H01L21/60 ,  H01L23/12 ,  H05K3/34

    CPC classification number: B23K1/0016 ,  B23K2201/42 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H05K3/244 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2203/054

    Abstract: PROBLEM TO BE SOLVED: To provide a wiring board including a conductor post which deals with high density assembly, and to provide a manufacturing method of the wiring board.SOLUTION: A wiring board 10 includes a conductor layer 12, a solder resist layer 13 laminated on the conductor layer 12, and a conductor post 16 which establishes electrical continuity with the conductor layer 12a disposed on the lower side of a through hole 131 provided at the solder resist layer 13. The solder resist layer 13 includes a thermosetting resin. The conductor post 16 is composed mainly of stannum, copper, or solder and has a lower conductor post 161 positioned in the through hole 131 and an upper conductor post 162 positioned on the lower conductor post 161 and extends toward the outside of the solder resist layer 13. At least a part of a lower end surface 162b of the upper conductor post 162 is closely in contact with an exterior surface 132 of the solder resist layer 13.

    Abstract translation: 要解决的问题：提供一种包括处理高密度组装的导体柱的布线板，并提供布线板的制造方法。 解决方案：布线板10包括导体层12，层叠在导体层12上的阻焊层13和导体柱16，其与设置在通孔的下侧的导体层12a建立导电性 设置在阻焊层13上。阻焊层13包括热固性树脂。 导体柱16主要由锡，铜或焊料组成，并且具有位于通孔131中的下导体柱161和位于下导体柱161上的上导体柱162，并且朝向阻焊层的外侧延伸 上导体柱162的下端表面162b的至少一部分与阻焊层13的外表面132紧密接触。版权所有：（C）2012，JPO＆INPIT

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