公开(公告)号：EP1472914B1

公开(公告)日：2008-04-09

申请号：EP03705923.5

申请日：2003-01-23

Applicant: Intel Corporation

Inventor： SATO, Daryl ,  BRIST, Gary ,  LONG, Gary

IPC: H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/0206 ,  H05K1/0219 ,  H05K1/0221 ,  H05K3/005 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: An apparatus that includes a plurality of metalized planes (202, 204), one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches (218, 220, 222) connecting to at least one of the plurality of metalized planes.

公开(公告)号：EP1770776A3

公开(公告)日：2007-12-05

申请号：EP06254920.9

申请日：2006-09-22

Applicant: TDK Corporation

Inventor： Kawabata, Kenichi, c/o TDK Corporation ,  Morita, Takaaki, c/o TDK Corporation

IPC: H01L23/538

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/544 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68368 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/92244 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/4652 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/1469 ,  H05K2203/166 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A semiconductor IC-embedded substrate suitable for embedding a semiconductor IC in which the electrode pitch is extremely narrow. The substrate comprises a semiconductor IC 120 in which stud bumps 121 are provided to the principal surface 120a, a first resin layer 111 for covering the principal surface 120a of the semiconductor IC 120, and a second resin layer 112 for covering the back surface 120b of the semiconductor IC 120. The stud bumps 121 of the semiconductor IC 120 protrude from the surface of the first resin layer 111. The method for causing the stud bumps 121 to protrude from the surface of the first resin layer 111 may involve using a wet blasting method to cause an overall reduction of the thickness of the first resin layer 111. The stud bumps 121 can thereby be properly uncovered even when the electrode pitch of the semiconductor IC 120 is narrow.

公开(公告)号：EP1827069A3

公开(公告)日：2007-10-03

申请号：EP07075315.7

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru, c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka, c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki, c/o Ibiden Co., Ltd. ,  Minoura, Hisashi, c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu, c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro, c/o Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A method of manufacturing a printed wiring board (210) comprising at least two insulating layers (211,212,213) made of a synthetic resin, an innerlayer conductor circuit (221-225) arranged between the insulating layers, and a plurality of blind via- holes (3A-3E) formed from an outermost surface toward the innerlayer conductor circuit (221-225) and having different depths by successively irradiating a laser beam every a portion forming the blind via-hole (3A-3E), characterized in that a shallowest blind via-hole (3A-3E) is formed as a standard hole by using a standard laser beam (242) having an energy strength required for the formation of the standard hole, and the standard laser beam (242) is irradiated plural times in the formation of the blind via-holes having deeper depths (3B,3D,3E).

Abstract translation: 一种制造包括至少两个由合成树脂制成的绝缘层（211,212,213）的印刷线路板（210）的方法，布置在绝缘层之间的内层导体电路（221-225）以及多个盲通孔（ 通过在形成盲通孔（3A-3E）的每个部分上连续照射激光束而从最外表面朝向内层导体电路（221-225）形成并且具有不同深度的多个通孔（3A-3E），其特征在于， 通过使用具有形成标准孔所需的能量强度的标准激光束（242）将通孔（3A-3E）形成为标准孔，并且标准激光束（242）被多次照射 形成深度更深的盲通孔（3B，3D，3E）。

公开(公告)号：EP1816905A3

公开(公告)日：2007-10-03

申请号：EP07075316.5

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru, c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka, c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki, c/o Ibiden Co., Ltd. ,  Minoura, Hisashi, c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu, c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro, c/o Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A printed wiring board (501) comprising two or more insulating layers (516,518) on an innerlayer conductor circuit (562), a via-hole (502) extending from an outermost surface of the insulating layer (516) through the two or more insulating layers (516,518) to the innerlayer conductor circuit (562) and an inner metal plated film (521) formed in the via-hole (502) so as to electrically connect to the innerlayer conductor circuit (562) to an outer conductor circuit (561) arranged on the outermost surface, characterized in that an annular dummy land (504) for reinforcement having an opening hole (540) around the via-hole (502) is arranged in a boundary portion (517) facing the two or more insulating layers (516,518) to each other and is joined to the inner metal plated film (521).

Abstract translation: 一种印刷电路板（501），包括位于内层导体电路（562）上的两个或更多个绝缘层（516,518），从绝缘层（516）的最外表面延伸穿过两个或更多个绝缘体 （562）的层（516,518）和形成在通孔（502）中的内部金属镀膜（521），以便将内层导体电路（562）电连接到外导体电路（561） ），其特征在于，在面向所述两个或更多个绝缘层（517）的边界部分（517）中布置用于加强的具有围绕所述通孔（502）的开口孔（540）的环形虚拟焊盘（504） （516,518）彼此接合并与内侧金属镀膜（521）接合。

公开(公告)号：EP0971570B1

公开(公告)日：2007-07-25

申请号：EP98901002.0

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： TAKADA, Masaru, Ibiden Co., Ltd. ,  TSUKADA, Kiyotaka, Ibiden Co., Ltd. ,  KOBAYASHI, Hiroyuki ,  MINOURA, Hisashi ,  UKAI, Yoshikazu ,  KONDO, Mitsuhiro

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: When a printed wiring board which has inner layer conductor circuits (161 and 131) between insulating layers (101 - 103) and blind via-holes (141 and 142) made from the top surface of the insulating layer to the inner layer conductor circuits is manufactured, a hole (160) is provided beforehand in the center part of the inner layer conductor circuits (161) at the bottom of the blind via-hole (141), and a laser beam is applied from the top surface side of the insulating layer to form the blind via-holes (141 and 142). After that, metal plating films are formed on the surfaces of the inner layer conductor circuits (131 and 161) and the blind via-holes (141 and 142).

Abstract translation: 当在绝缘层（101-103）之间具有内层导体电路（161和131）以及由绝缘层的顶面到内层导体电路制成的盲通孔（141和142）的印刷线路板是 在盲孔（141）的底部的内层导体电路（161）的中央部预先设置孔（160），从绝缘体的上表面侧照射激光 层以形成盲通孔（141和142）。 此后，在内层导体电路（131和161）和盲通孔（141和142）的表面上形成金属镀膜。

公开(公告)号：EP0964610B1

公开(公告)日：2006-11-22

申请号：EP99304260.5

申请日：1999-06-01

Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.

Inventor： Gaku, Morio, Mitsubishi Gas Chemical Company, Inc. ,  Ikeguchi, Nobuyuki, Mitsubishi Gas Chemical Co,Inc ,  Tanaka, Yasuo, Mitsubishi Gas Chemical Co., Inc.

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/429 ,  B23K26/389 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/385 ,  H05K2201/0112 ,  H05K2201/0215 ,  H05K2201/0323 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2203/0315 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49165

公开(公告)号：EP1478215A3

公开(公告)日：2006-02-08

申请号：EP04394023.8

申请日：2004-05-07

Applicant: Nortel Networks Limited

Inventor： Difilippo, Luigi ,  Wyrzykowska, Aneta ,  Kwong, Herman

IPC: H05K3/30 ,  H05K3/46

CPC classification number: H05K1/112 ,  H01L2224/14 ,  H01L2224/17 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A method for implementing a circuit component (160) on a surface of a multilayer circuit board (110) is provided. The circuit component includes a plurality of pins (162,164,166,168,170,172,174,176) and the circuit board (110) includes a plurality of electrically conductive vias (142,148,150,152,156) penetrating at least one layer of the circuit board (110) and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board (110). The method comprises the step of forming at least one pin (162,168A,170A,172,176A) of the plurality of pins (162,164,166,168,170,172,174,176) of the circuit component (160) to have a length compatible with a depth of a corresponding via (142,148,150,152,156) of the circuit board (110).

Abstract translation: 提供一种在多层电路板（110）的表面上实现电路部件（160）的方法。 电路部件包括多个引脚（162,164,166,168,170,172,174,176），并且电路板（110）包括穿透电路板（110）的至少一个层的多个导电通孔（142,148,150,152,156），并布置成形成至少一个 通道，用于在电路板（110）的一个或多个信号层处布线一个或多个迹线。 该方法包括形成电路部件（160）的多个引脚（162,164,166,168,170,172,174,176）的至少一个引脚（162,168A，170A，172,176A）以使其长度与对应的通孔（142,148,150,152,156）的深度相兼容的步骤， 的电路板（110）。

公开(公告)号：EP1196016A3

公开(公告)日：2004-06-30

申请号：EP01123229.5

申请日：2001-10-02

Applicant: Hitachi, Ltd.

Inventor： Itabashi, Takeyuki ,  Akahoshi, Haruo ,  Takai, Eiji ,  Nishimura, Naoki ,  Iida, Tadashi ,  Ueda, Yoshinori, Hitachi Horiyamashita Apt. D-22

IPC: H05K3/42 ,  C23C18/40

CPC classification number: C23C18/40 ,  H05K3/421 ,  H05K3/422 ,  H05K3/426 ,  H05K3/429 ,  H05K2201/09518

Abstract: Providing a multilayer wiring substrate high in connection reliability through process steps of forming more than one opening (3) such as a via-hole in a dielectric layer (2) laminated on a substrate (1) and then applying uniform copper plating (4) to a surface portion of the dielectric layer including the opening to thereby form a wiring layer. An electroless copper plating solution with at least one of mandelonitrile and triethyltetramine mixed therein is used to perform the intended electroless copper plating. An alternative way of performing such electroless copper plating is to make use of an electroless copper plating solution with chosen additive agents or "admixtures" containing at least one of mandelonitrile and triethyltetramine plus eriochrome black T along with at least one of 2,2'-bipyridyl, 1,10-phenanthroline, and 2,9-dimethyl-1,10-phenanthroline.

公开(公告)号：EP0964610A3

公开(公告)日：2001-03-21

申请号：EP99304260.5

申请日：1999-06-01

Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.

Inventor： Gaku, Morio, Mitsubishi Gas Chemical Company, Inc. ,  Ikeguchi, Nobuyuki, Mitsubishi Gas Chemical Co,Inc ,  Tanaka, Yasuo, Mitsubishi Gas Chemical Co., Inc.

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/429 ,  B23K26/389 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/385 ,  H05K2201/0112 ,  H05K2201/0215 ,  H05K2201/0323 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2203/0315 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed are a printed wiring board having micro-via holes highly reliable for conduction and a method of making the micro-via hole by providing a coating or sheet (a) of an organic substance containing 3 to 97% by volume of at least one selected from a metal compound powder, a carbon powder or a metal powder having a melting point of at least 900°C and a bond energy of at least 300kJ/mol on a copper foil as an outermost layer of a copper-clad laminate having at least two copper layers (b), or providing a coating or sheet (a) of the same after oxidizing a copper foil as an outermost layer, irradiating the coating or sheet with a carbon dioxide gas laser (d) at an output of 20 to 60mJ/pulse, thereby removing a micro-via-hole-forming portion of at least the copper foil as the outermost layer, then irradiating micro-via-hole-forming portions of the remaining layers (c) with a carbon dioxide gas laser (f) at an output of 5 to 35mJ/pulse to make a micro-via hole which does not penetrate through the copper foil (g) in a bottom of the micro-via hole, and electrically connecting the copper foil as the outermost layer and the copper foil in the bottom (g) of the micro-via hole with a metal plating (h) or an electrically conductive coating composition.

Abstract translation: 本发明公开了具有高导电可靠性的微通孔的印刷线路板和通过提供包含3至97体积％的至少一种选择的有机物质的涂层或片材（a）来制造微通孔的方法 由作为覆铜层压板的最外层的铜箔上的金属化合物粉末，具有至少900℃的熔点和至少300kJ / mol的结合能的碳粉末或金属粉末，至少具有 两个铜层（b），或者在氧化作为最外层的铜箔之后提供它们的涂层或片材（a），用二氧化碳气体激光器（d）以20-60mJ的输出辐照涂层或片材 /脉冲，由此除去至少作为最外层的铜箔的微过孔形成部分，然后用二氧化碳气体激光器（f）照射其余层（c）的微过孔形成部分 ）以5至35mJ /脉冲的输出来形成不穿透t的微通孔 通过微通孔底部的铜箔（g），用金属镀层（h）电连接作为最外层的铜箔和微通孔底部（g）中的铜箔， 或导电涂料组合物。

公开(公告)号：EP1014769A3

公开(公告)日：2000-10-18

申请号：EP99310466.0

申请日：1999-12-23

Applicant: VICTOR COMPANY OF JAPAN, LTD.

Inventor： Seki, Yasuaki ,  Shiratori, Shigenori ,  Suzuki, Kenji

IPC: H05K3/46

CPC classification number: H05K3/4673 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2203/0759 ,  H05K2203/085 ,  H05K2203/1105 ,  Y10T428/24917 ,  Y10T428/31681 ,  Y10T428/31728

Abstract: In a manufacturing method of a printed circuit board comprising a process of coating insulative resin on a surface of a printed circuit board having a blind hole and a process of filling up the insulative resin in the blind hole, the printed circuit board coated with the insulative resin is kept in a low pressure atmosphere of 1.3 to 666 hPa, and then the insulative resin is hardened, so that the insulative resin is filled up in the blind hole appropriately.