公开(公告)号：EP1143379A1

公开(公告)日：2001-10-10

申请号：EP01400857.7

申请日：2001-04-03

Applicant: SAGEM SA

Inventor： Darnault, Patrick

IPC: G06K19/077

CPC classification number: G06K19/07769 ,  G06K19/07743 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49109 ,  H01L2924/01057 ,  H05K3/0047 ,  H05K3/321 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10719 ,  H05K2201/10727 ,  H05K2203/0207 ,  H01L2924/00014 ,  H01L2924/00

Abstract: On réalise une carte à puce (1) mixte selon deux procédés. La carte à puce comporte deux couches (1.1,1.2) entre lesquelles se loge un circuit électrique secondaire (1.3). Un micromodule (2), encastré dans la carte réalise un circuit électrique principal. Ce circuit électrique principal joue le rôle d'interface avec un lecteur de carte à puce. Des puits de connexion (13,14) entre les deux circuits ne sont pas réalisés de la même façon et au même moment selon chaque procédé. Mais finalement ils sont remplis de colle conductrice qui permet d'établir des connexions entre les deux circuits. On propose ainsi deux procédés de réalisation de cartes mixtes dont un permet notamment d'améliorer le taux de réussite des connexions entre un circuit principal défini par un micromodule et un circuit d'une couche enterrée de la carte.

Abstract translation: 该卡具有第一绝缘层（1.2），其上具有次级电路层。 第二绝缘层覆盖次级电路（1.3）。 在该第二绝缘层中钻出孔（13,14），并填充导电胶。 电子模块（2）设置在该第二绝缘层中的空腔中，并且导电胶与模块上的两个点接触。

公开(公告)号：EP1105838A1

公开(公告)日：2001-06-13

申请号：EP00951232.8

申请日：2000-06-27

Applicant: Orga Kartensysteme GmbH

Inventor： ISBERNER, Roland

IPC: G06K19/077

CPC classification number: G06K19/07747 ,  G06K19/07745 ,  H01L23/3121 ,  H01L23/49855 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/181 ,  H05K1/183 ,  H05K3/305 ,  H05K2201/0129 ,  H05K2201/10477 ,  H05K2201/10727 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099

Abstract: The invention relates to a support element for an integrated circuit module to be fitted in a chip card comprising: a plate-shaped support body on whose one front flat side metallic contact surfaces are arranged, and on whose rear flat side the integrated circuit module is arranged; a protective layer which covers the integrated circuit module and which is made of an encapsulating material, and; an adhesive surface which is applied to the rear of the support body and which is provided for fastening the support element to the chip card. According to the invention, the adhesive layer covers the entire rear surface of the support element as an all-over adhesive layer. This inventive embodiment enables the production costs of said support elements to be significantly reduced. The invention also relates to a method for producing such a support element in which the all-over adhesive layer is attached to the support element by a pressing process effected by a pressing device having a pressing surface that is made of an elastic material. The pressing surface is flexible enough to permit the support element to submerge, in an all-over manner with the rear thereof which is provided with the integrated circuit module and with the protective layer that covers the same, into the pressing surface.

公开(公告)号：EP1099361A1

公开(公告)日：2001-05-16

申请号：EP99930884.4

申请日：1999-07-09

Applicant: Oak-Mitsui, Inc.

Inventor： CARBIN, Derek ,  HERRICK, Wendy, A.

IPC: H05K3/02 ,  H05K3/38 ,  H05K3/10

CPC classification number: H05K3/025 ,  H05K3/108 ,  H05K3/384 ,  H05K3/4652 ,  H05K2201/0317 ,  H05K2201/0344 ,  H05K2201/0355 ,  H05K2201/10477 ,  H05K2203/0152 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K2203/0726 ,  Y10T29/49155

Abstract: A method of forming circuit lines on a substrate by applying a roughened conductive metal layer using a copper foil carrier. The copper foil is etched away, leaving the roughened conductive metal embedded in the surface of the substrate. The conductive metal may be treated to remove an oxide layer. A photoresist may also be applied over the treated conductive metal layer to define a fine line circuit pattern. The photoresist defining the fine line circuit pattern is then removed to expose trenches in accordance with the desired circuit pattern. Copper is applied into the trenches over the exposed conductive metal, and the remaining photoresist, and conductive metal underlying the remaining photoresist, is removed to finish the fine line circuit pattern.

公开(公告)号：EP1093082A2

公开(公告)日：2001-04-18

申请号：EP00307934.0

申请日：2000-09-13

Applicant: FUJITSU LIMITED

Inventor： Kaiya, Hiroshi, c/o Fujitsu Limited ,  Honda, Toshiyuki, c/o Fujitsu Limited

IPC: G06K19/077

CPC classification number: G06K19/07747 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/07769 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/182 ,  H05K3/321 ,  H05K3/3436 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10666 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A module of a combination card can be incorporated into a card body with solder being easily melted, and heat transmission to portions other than the antenna connection terminals is reduced. A card body (1) is provided with an antenna. The module (20) includes a substrate (7) which has a terminal surface on which at least one external connection terminal (4) is formed and a mounting surface opposite to the terminal surface. An IC chip (8) is mounted on the mounting surface. The module includes at least one antenna connection terminal (21a, 21b) located on the mounting surface. The antenna connection terminal (21a) is connected to the antenna, and at least a part (21b) of the antenna connection terminal (21a, 21b) is exposed on the terminal surface.

Abstract translation: 组合卡的模块​​可以结合到卡体中，焊料容易熔化，并且对天线连接端子以外的部分的热传递减少。 卡体（1）设置有天线。 模块（20）包括：基板（7），其具有形成有至少一个外部连接端子（4）的端子表面和与端子表面相对的安装表面。 IC芯片（8）安装在安装面上。 模块包括位于安装表面上的至少一个天线连接端子（21a，21b）。 天线连接端子（21a）连接到天线，并且天线连接端子（21a，21b）的至少一部分（21b）暴露在端子表面上。

公开(公告)号：EP0986099A2

公开(公告)日：2000-03-15

申请号：EP99306922.8

申请日：1999-08-31

Applicant: LUCENT TECHNOLOGIES INC.

Inventor： Degani, Yinon ,  Dudderar, Thomas Dixon ,  Frye, Robert Charles ,  Tai, King Lien

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15173 ,  H05K2201/10477

Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The translator also has a large area outboard of the IC chip area to allow fan out from high pin count chips to large pitch interconnection sites for interconnection to the next board level.

Abstract translation: 该说明书描述了一种嵌入式芯片IC封装，其中IC芯片与转换器结合，并且用于IC电源和接地互连的电源和接地层形成在转换器的不同互连层上。 转换器的多电平互联能力允许交叉，并允许IC芯片的电源和接地引脚与信号I / O隔离，并且整合到更少的互连到下一个电路板级。 翻译器还具有IC芯片面积大的外部面积，可以将风扇从高引脚数芯片到大间距互连位置互连到下一个板级。

公开(公告)号：EP0977298A2

公开(公告)日：2000-02-02

申请号：EP99114940.2

申请日：1999-07-30

Applicant: Kyocera Corporation

Inventor： Sawa, Yoshinobu, c/o Kyocera Corporation ,  Koriyama, Shinichi, c/o Kyocera Corporation ,  Kitazawa, Kenji, c/o Kyocera Corporation ,  Minamiue, Hidehiro, c/o Kyocera Corporation

IPC: H01P1/04

CPC classification number: H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/05599 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/1903 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P1/047 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/142 ,  H05K3/0061 ,  H05K2201/09781 ,  H05K2201/10477 ,  H05K2201/1053 ,  H05K2201/10727 ,  H05K2203/1572 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: There is described a high-frequency module comprising a high-frequency device-mounting package and an external circuit board characterized in that said high-frequency device-mounting package (A) includes a dielectric substrate (1) having a first grounding layer (4) contained therein, said dielectric substrate (1) mounting a high-frequency device (2) on one surface thereof and having, formed on one surface thereof, first high-frequency signal transmission lines (3) connected to said high-frequency device (2), and having, formed on the other surface thereof, second high-frequency signal transmission lines (7) coupled to said first high-frequency signal transmission lines (3), said external circuit board (B) is constituted by a dielectric board (20) having third high-frequency signal transmission lines (25) and a second grounding layer (26), said third high-frequency signal transmission lines (25) being formed on one surface of said dielectric board (20), and said second grounding layer (26) being formed on the other surface of said dielectric board (20) or inside thereof; and said high-frequency device-mounting package (A) and said external circuit board (B) are arranged side by side, and the second high-frequency signal transmission lines (7) of the high-frequency device-mounting package (A) are electrically connected to the third high-frequency signal transmission lines (25) of the external circuit board (B) through linear electrically conducting members (31). The patterns of the second high-frequency signal transmission lines on the side of the high-frequency device-mounting package can be easily aligned with the patterns of the third high-frequency signal transmission lines on the side of the external circuit board, effectively reducing the transmission loss at the junction portions of the lines.

Abstract translation: 描述了一种包括高频器件安装封装和外部电路板的高频模块，其特征在于，所述高频器件安装封装（A）包括具有第一接地层（4）的电介质衬底（1） ），所述电介质基板（1）在其一个表面上安装有高频装置（2），并且在其一个表面上形成有连接到所述高频装置（2）的第一高频信号传输线（3） 2）上，并且在其另一表面上形成有与所述第一高频信号传输线（3）耦合的第二高频信号传输线（7），所述外部电路板（B）由介电板 （20），其具有第三高频信号传输线（25）和第二接地层（26），所述第三高频信号传输线（25）形成在所述介电板（20）的一个表面上，并且所述第二高频信号传输线 接地层（ 26）形成在所述介电板（20）的另一个表面上或其内部; （A）和所述外部电路板（B）并排布置，并且所述高频器件安装封装（A）的所述第二高频信号传输线（7）与所述高频器件安装封装（A） 通过线状导电部件（31）与外部电路基板（B）的第三高频信号传输线路（25）电连接。 高频器件组装侧的第二高频信号传输线的图案可以容易地与外部电路板侧的第三高频信号传输线的图案对齐，从而有效地减少 线路连接部分的传输损耗。

公开(公告)号：EP0766909A4

公开(公告)日：1997-10-22

申请号：EP95923676

申请日：1995-06-08

Applicant: CUBIC MEMORY

Inventor： PEDERSEN DAVID V ,  FINLEY MICHAEL G ,  SAUTTER KENNETH M

IPC: H01L25/00 ,  H01L21/60 ,  H01L21/98 ,  H01L23/373 ,  H01L23/482 ,  H01L23/485 ,  H01L23/52 ,  H01L23/525 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L29/06 ,  H01R4/04 ,  H01R29/00 ,  H05K3/30 ,  H05K3/32 ,  H05K7/02 ,  H05K7/06

CPC classification number: H01L24/81 ,  H01L23/3737 ,  H01L23/4824 ,  H01L23/5256 ,  H01L23/5328 ,  H01L23/5382 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/13 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32145 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01R4/04 ,  H01R29/00 ,  H05K3/305 ,  H05K3/321 ,  H05K7/023 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10719 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099

Abstract: A method and apparatus for vertically interconnecting stacked silicon segments (36) is disclosed. Each segment (36) includes a plurality of adjacent dies on a semiconductor wafer. The plurality of dies on a segment are interconnected using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads (42) for external electrical connection points. Each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls (102) on each of the segments (36). After the segments are cut from the wafer, the segments are placed on top of one another to form a stack (112). Vertically adjacent segments (36) in the stack (112) are electrically interconnected by applying electrically conductive epoxy traces (130) to all four sides of the stack. The inwardly sloping edge walls (102) of each of the segments (36) in the stack (112) provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked.

公开(公告)号：EP0766909A1

公开(公告)日：1997-04-09

申请号：EP95923676.0

申请日：1995-06-08

Applicant: CUBIC MEMORY

Inventor： PEDERSEN, David, V. ,  FINLEY, Michael, G. ,  SAUTTER, Kenneth, M.

IPC: H01L25 ,  H01L21 ,  H01L23 ,  H01R4 ,  H01R29 ,  H05K3 ,  H05K7 ,  H01L29

CPC classification number: H01L24/81 ,  H01L23/3737 ,  H01L23/4824 ,  H01L23/5256 ,  H01L23/5328 ,  H01L23/5382 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/13 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32145 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01R4/04 ,  H01R29/00 ,  H05K3/305 ,  H05K3/321 ,  H05K7/023 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10719 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099

Abstract: A method and apparatus for vertically interconnecting stacked silicon segments (36) is disclosed. Each segment (36) includes a plurality of adjacent dies on a semiconductor wafer. The plurality of dies on a segment are interconnected using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads (42) for external electrical connection points. Each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls (102) on each of the segments (36). After the segments are cut from the wafer, the segments are placed on top of one another to form a stack (112). Vertically adjacent segments (36) in the stack (112) are electrically interconnected by applying electrically conductive epoxy traces (130) to all four sides of the stack. The inwardly sloping edge walls (102) of each of the segments (36) in the stack (112) provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked.

Abstract translation: 公开了用于垂直互连堆叠的硅片段（36）的方法和装置。 每个区段（36）在半导体晶片上包括多个相邻的管芯。 段上的多个管芯使用延伸到段的所有四个侧面的一层或多层金属互连来互连，以提供用于外部电连接点的边缘接合焊盘（42）。 使用斜面切割从晶片的背面切割每个段，以在每个段（36）上提供四个向内倾斜的边缘壁（102）。 在从晶片上切下片段之后，片段被放置在彼此的顶部以形成堆叠（112）。 通过将导电环氧树脂迹线（130）施加到堆叠的所有四个侧面来使堆叠（112）中的垂直相邻的段（36）电互连。 堆叠（112）中的每个段（36）的向内倾斜的边缘壁（102）提供了凹槽，该凹槽允许导电环氧树脂一旦堆叠段堆叠就接近每个段上的边缘接合焊盘和横向电路 。

公开(公告)号：EP0421343A2

公开(公告)日：1991-04-10

申请号：EP90118860.7

申请日：1990-10-02

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Makino, Yutaka ,  Ishimoto, Kazumi ,  Izumi, Yasuo ,  Kitayama, Yoshifumi ,  Kumagai, Koichi

IPC: H01L23/552 ,  H01L23/498

CPC classification number: H05K1/181 ,  H01L23/49534 ,  H01L23/4985 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K2201/09481 ,  H05K2201/10477 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10681 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor element package (P) and a semiconductor element package mounting distributing circuit basic plate, wherein the shield metallic layer (60) is provided on the flexible insulating basic plate for constituting the package, so that the semiconductor element (30) mounted on the flexible insulating basic plate (10) may be kept electromagnetically shielded positively with the shield metallic layer, whereby troublesome operation such as mounting the bulk high box shaped electromagnetic shield member on the outside of the semiconductor element package mounted on the distributing circuit basic plate as in the conventional one is not required, and, also, since the shield metallic layer is provided on the face, which is not formed with the lead patterns, of the flexible insulating basic plate, no influences are applied at all upon the construction of the land pattern and the mounting construction of the semiconductor element.

Abstract translation: 一种半导体元件封装和半导体元件封装件安装分配电路基本板，worin屏蔽金属层为构成封装设置在挠性绝缘基本板，所以没有安装在柔性绝缘基底板的半导体元件可以电磁保持屏蔽 正与屏蔽金属层，由此麻烦术：如散装高盒状的电磁波屏蔽部件安装在半导体元件封装的外侧安装在所述分配电路基本板作为在不需要传统的一个，并且，因此，由于 设置在面对所述屏蔽金属层，所有这些不与引线图案而形成，所述柔性绝缘基底板的，没有影响在所有在所述焊盘图案的结构和半导体元件的安装结构的应用。

公开(公告)号：EP0420604A1

公开(公告)日：1991-04-03

申请号：EP90310520.3

申请日：1990-09-26

Applicant: MOTOROLA, INC.

Inventor： Leicht, John Laurence

IPC: H01R4/04 ,  H05K1/14

CPC classification number: H05K3/321 ,  H01R4/04 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/10378 ,  H05K2201/10477 ,  H05K2201/10719 ,  H05K2201/10727 ,  H05K2201/10977 ,  H05K2203/167

Abstract: An adhesive interconnection device of Figure 2 (115) providing a simplified simultaneous electrical and mechanical interconnection using one preformed member, comprised of a pattern of non-pressure activated electrically conductive adhesive members (140) and nonconductive adhesive members (145), which must be aligned with the conductive pads of at least two planar electrical devices (100 and 105). Sandwiching the device (115) between at least two electrical devices causes simultaneous electrical conduction paths and mechanical bonds (230) between the two electrical devices. An additional heat curing step may be introduced to achieve the proper conductivity level in the electrically conductive members required for a specific application.

Abstract translation: 图2的（115）提供使用由非压力的图案的一个预成型件的简化同时电气和机械互连的粘合剂互连设备中启动的导电粘接部件（140）和非导电粘接件（145）必须被 具有至少两个平面的电气设备（100和105）的导电垫对齐。 至少两个电装置之间夹持所述装置（115）使两个电设备之间的同时导电路径和机械键（230）。 附加的热固化步骤可以被引入以实现特定应用所需的导电构件的适当的导电性水平。