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412 records (took 0.021 seconds)

    151.
    发明专利
    未知

    公开(公告)号：DE69224827D1

    公开(公告)日：1998-04-23

    申请号：DE69224827

    申请日：1992-05-28

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： PALARA SERGIO

    IPC: H01L29/06 ,  H01L29/40 ,  H01L29/8605 ,  H01L29/86

    Abstract: A spiral resistor (1), being of a type formed on a semiconductor substrate (2) to withstand high voltages, comprises at least one thin field-plate layer (6) covering said substrate (2) between adjacent turns (5) of the resistor. This prevents the well-known phenomenon of the "phantom gate" from occurring which would result in the characteristics of spiral resistors deteriorating over time.

    152.
    发明专利
    未知

    公开(公告)号：DE69313837T2

    公开(公告)日：1998-04-09

    申请号：DE69313837

    申请日：1993-06-09

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： RUSSO BIAGIO ,  POLUZZI RINALDO ,  LUZZI CLAUDIO

    IPC: G06F9/44 ,  G05B13/02 ,  G06F1/035 ,  G06N7/02 ,  G06N7/04 ,  G06F15/76 ,  G06F7/60

    Abstract: A method for setting up the memory of an electronic controller operates in Fuzzy logic, whereby predetermined membership functions (f(m)) of logic variables (M), defined within a universe of discourse (U) sampled in a finite number of points (m), are subjected to inference operations basically configured by IF/THEN rules with at least one front preposition and at least one rear implication. The controller further comprises a central control unit (3) provided with a memory section (5) for storing predetermined values (l) of the membership functions (f(m)) which appear in the front or IF part of the Fuzzy rules and have a predetermined degree of truth or membership (G). This method provides for storing into said memory section (5) the only values (l) of those membership functions (f(m)) which have a value (l) of the degree of membership (G) other than zero at the points (m) of the universe of discourse (U).

    158.
    发明专利
    未知

    公开(公告)号：DE69400916T2

    公开(公告)日：1997-04-03

    申请号：DE69400916

    申请日：1994-07-01

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： TRAVAGLIA FREDERICO ,  LA ROSA MARIA GRAZIA ,  GIARRIZZO GUIDO

    IPC: H03L7/08 ,  G06F9/44 ,  G06N7/02 ,  H03L7/10

    Abstract: A phase-lock loop circuit (1) with fuzzy control, which comprises a phase comparator (2) whose output is connected to a low-pass filter (3) that is suitable to drive a voltage-controlled oscillator (4); the phase comparator (2) is suitable to generate a signal (z) that represents the phase difference between an input signal (x) and a signal (y) generated by the oscillator. The particularity of the invention resides in the fact that the oscillator (4) is furthermore driven by a control signal (Vinj) generated by fuzzy control means (5) the input whereof is the signal (z) representing the phase difference.

    159.
    发明专利
    未知

    公开(公告)号：DE69122598T2

    公开(公告)日：1997-03-06

    申请号：DE69122598

    申请日：1991-12-18

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PUZZOLO SANTO ,  ZAMBRANO RAFFAELE ,  PAPARO MARIO

    IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L21/82

    Abstract: In the version with unisolated components the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer; the low voltage bipolar transistor is indeed situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In the version with isolated components, in an n- epitaxial layer there are two p+ regions, i.e. the first, constituting the power transistor base, encloses the n+ emitter region of said transistor while the second encloses two n+ regions and one p+ region constituting the collector, emitter and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

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