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    MEMS DEVICE HAVING A GETTER
    171.
    发明公开
    MEMS DEVICE HAVING A GETTER 有权
    MEMS-VORRICHTUNG MIT EINEM GETTER

    公开(公告)号：EP2973685A4

    公开(公告)日：2016-10-12

    申请号：EP14774321

    申请日：2014-03-13

    Applicant: BOSCH GMBH ROBERT

    Inventor： SAMARAO ASHWIN ,  O'BRIEN GARY ,  FEYH ANDO ,  YAMA GARY ,  GRAHAM ANDREW ,  KIM BONGSANG ,  PURKL FABIAN

    IPC: H01L23/12 ,  B81B7/02 ,  H01L21/322

    CPC classification number: B81C1/00285 ,  B81C2201/0115 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/035 ,  H01L21/3223 ,  H01L21/3225 ,  H01L23/28

    Abstract: A microelectromechanical system (MEMS) device includes a high density getter. The high density getter includes a silicon surface area formed by porosification or by the formation of trenches within a sealed cavity of the device. The silicon surface area includes a deposition of titanium or other gettering material to reduce the amount of gas present in the sealed chamber such that a low pressure chamber is formed. The high density getter is used in bolometers and gyroscopes but is not limited to those devices.

    Abstract translation: 微机电系统（MEMS）装置包括高密度吸气剂。 高密度吸气剂包括通过孔化形成的硅表面积或者通过在器件的密封空腔内形成沟槽。 硅表面积包括钛或其它吸气材料的沉积物以减少存在于密封室中的气体的量，从而形成低压室。 高密度吸气剂用于测辐射热计和陀螺仪，但不限于这些设备。

    Procédé de fabrication d'une structure micromécanique et/ou nanomécanique comportant une surface poreuse
    173.
    发明公开
    Procédé de fabrication d'une structure micromécanique et/ou nanomécanique comportant une surface poreuse 有权
    一种用于生产微或纳米机械结构，其包括多孔表面的方法

    公开(公告)号：EP2767504A1

    公开(公告)日：2014-08-20

    申请号：EP14155613.4

    申请日：2014-02-18

    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

    Inventor： Ollier, Eric

    IPC: B81C1/00

    CPC classification number: B81C1/00515 ,  B81C1/00206 ,  B81C1/00412 ,  B81C1/00626 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/038

    Abstract: Procédé de fabrication d'une structure micromécanique et/ou nanomécanique comportant les étapes à partir d'un élément comportant un substrat support et une couche sacrificielle :
    a) formation d'une première couche dont au moins une partie est poreuse,
    b) formation, sur la première couche, d'une couche en un (ou plusieurs) matériau(x) assurant les propriétés mécanique de la structure, dite couche intercalaire,
    c) formation, sur la couche intercalaire, d'une deuxième couche dont au moins une partie est poreuse,
    d) formation de ladite structure dans l'empilement de la première couche, de la couche intercalaire et de la deuxième couche,
    e) libération de ladite structure par retrait au moins partielle de la couche sacrificielle.

    Abstract translation: 该方法包括：形成第一层，即 硅层（6），其一部分是多孔的，并且在所述第一层上的层间（16）形成，以确保结构的机械性能。 第二层被形成在层间，其中所述第二层的一部分是多孔的上。 在第一层中，层间和第二层，其中第一层和第二层由多孔硅锗和在层间的由非多孔硅锗的堆叠的结构被形成。 该结构是通过牺牲层（4）的部分撤回释放。

    APPARATUS AND METHODS FOR UNIFORMLY FORMING POROUS SEMICONDUCTOR ON A SUBSTRATE
    174.
    发明公开
    APPARATUS AND METHODS FOR UNIFORMLY FORMING POROUS SEMICONDUCTOR ON A SUBSTRATE 有权
    装置及其制造方法均匀的多孔SEMICONDUCTORS在基底上

    公开(公告)号：EP2652774A2

    公开(公告)日：2013-10-23

    申请号：EP11876396.0

    申请日：2011-11-03

    Applicant: Solexel, Inc.

    Inventor： KRAMER, Karl-Josef ,  MOSLEHI, Mehrdad, M. ,  TAMILMANI, Subramanian ,  KAMIAN, George ,  ASH-JAEE, Jay ,  YONEHARA, Takao

    IPC: H01L21/3063 ,  H01L21/306 ,  H01L21/02

    CPC classification number: B81C99/0025 ,  B81C2201/0115 ,  C25D11/005 ,  C25D11/32 ,  C25D17/001 ,  C25D17/06 ,  C25F3/12 ,  C25F7/00 ,  H01L21/306 ,  H01L31/0284 ,  H01L31/18

    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

    Abstract translation: 本公开允许均匀的多孔半导体层的高生产率制造控制（由单层或多层的多孔半导体的：如多孔硅，其包括单个孔隙率或多层多孔性的层）。 一些应用包括MEMS分离的制造和用于分离和MEMS器件制造中，膜形成和浅沟槽隔离（STI）多孔硅（使用在最佳孔隙率的多孔硅的形成和随后的氧化）的牺牲层。 此外，本发明适用于的光伏，MEMS，传感器的一般字段和致动器，包括，独立的，或与集成半导体微电子，半导体微电子和光电子芯片集成在一起。

    FORMATION OF NANOPOROUS MATERIALS
    175.
    发明公开
    FORMATION OF NANOPOROUS MATERIALS 审中-公开
    制备纳米多孔材料

    公开(公告)号：EP2367969A1

    公开(公告)日：2011-09-28

    申请号：EP09831303.4

    申请日：2009-12-08

    Applicant: University Of South Australia

    Inventor： LOSIC, Dusan

    IPC: C25C3/00 ,  C25C5/00 ,  C25D1/16 ,  C25B9/06 ,  C25C7/00 ,  H01M4/04 ,  C25C3/06 ,  C25D1/00 ,  C25C3/20 ,  C25D1/08

    CPC classification number: C25D1/08 ,  B81C1/00047 ,  B81C2201/0114 ,  B81C2201/0115 ,  C25D1/00 ,  C25D1/006 ,  C25D11/02 ,  C25D11/045

    Abstract: A process for forming a porous metal oxide or metalloid oxide material, the process including: - providing an anodic substrate including a metal or metalloid substrate;- providing a cathodic substrate; - contacting the anodic substrate and the cathodic substrate with an acid electrolyte to form an electrochemical cell; - applying an electrical signal to the electrochemical cell;- forming shaped pores in the metal or metalloid substrate by: (c) time varying the applied voltage of the electrical signal to provide a voltage cycle having a minimum voltage period during which a minimum voltage is applied, a maximum voltage period during which a maximum voltage is applied, and a transition period between the minimum voltage period and the maximum voltage period, wherein the voltage is progressively increased from the minimum voltage to the maximum voltage during the transition period, or (d) time varying the current of the electrical signal to provide a current cycle having a minimum current period during which a minimum current is applied, a maximum current period during which a maximum current is applied, and a transition period between the minimum current period and the maximum current period, wherein the voltage is progressively increased from the minimum current to the maximum current during the transition period.

    Semiconductor substrate comprising at least a buried insulating cavity
    177.
    发明公开
    Semiconductor substrate comprising at least a buried insulating cavity 审中-公开
    Halbleitersubstrat mit mindestens einem vergrabenen Hohlraum

    公开(公告)号：EP2280412A2

    公开(公告)日：2011-02-02

    申请号：EP10184095.7

    申请日：2002-11-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

    IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81C1/00

    CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

    Abstract: A semiconductor substrate comprising at least a buried insulating cavity (10b, 10d) and comprising:
    - a semiconductor substrate (7) having a first type of concentration and having a plurality of trenches (8, 10),
    - a surface layer (7a, 9a) on said semiconductor substrate (7) in order to close superficially said plurality of trenches (8, 10) forming said at least a buried insulating cavity (10b, 10d);
    - a first semiconductor material layer (9) on said surface layer (7a, 9a) having the same first type of concentration as said semiconductor substrate (7), said first semiconductor material layer (9) comprising at least a trench (11) which is in communication with said at least a buried insulating cavity (10b, 10d).

    Abstract translation: 1.一种半导体衬底，包括至少一个掩埋绝缘腔（10b，10d），并且包括：具有第一类型的半导体衬底（7）并具有多个沟槽（8,10）， - 表面层（7a， 以形成所述至少一个掩埋绝缘腔（10b，10d）的所述多个沟槽（8,10）的表面封闭; - 在所述表面层（7a，9a）上具有与所述半导体衬底（7）相同的第一类型的第一半导体材料层（9），所述第一半导体材料层（9）至少包括沟槽（11），所述沟槽 与所述至少一个掩埋绝缘腔（10b，10d）连通。

    VERFAHREN ZUR HERSTELLUNG EINES BAUTEILS UND SENSORELEMENT
    179.
    发明公开
    VERFAHREN ZUR HERSTELLUNG EINES BAUTEILS UND SENSORELEMENT 有权
    用于测量相对压力和制造工艺的传感器元件

    公开(公告)号：EP2125607A1

    公开(公告)日：2009-12-02

    申请号：EP07847470.7

    申请日：2007-11-28

    Applicant: Robert Bosch GmbH

    Inventor： KRAMER, Torsten ,  KNESE, Kathrin ,  BENZEL, Hubert ,  SCHUERMANN, Gregor ,  ARMBRUSTER, Simon ,  SCHELLING, Christoph

    IPC: B81C1/00 ,  G01L9/00

    CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2207/015 ,  B81C2201/0115 ,  G01L19/0038

    Abstract: The present invention proposes a method for the production of a component (10), comprising at least one membrane (11) configured in the component surface, the membrane spanning a cavern (12), and further comprising at least one access opening (14) to the cavern (12) coming from the component rear, wherein at least one first membrane layer (2) and the cavern (12) are created in a monolithic semiconductor substrate (1) starting from the component surface, and wherein the access opening (14) starting from the substrate rear is created in a chronologically limited etching process. For this purpose, according to the invention the access opening (14) is disposed in a region in which the substrate material reaches the first membrane layer (2). Further, the etching process comprises at least one anisotropic etching step and at least one isotropic etching step for creating the access opening (14), wherein an etching channel (15) is created starting at the substrate rear in the anisotropic etching step, the channel ending beneath the first membrane layer (2) in the surrounding region of the cavern (12), and wherein at least the and region (16) of this etching channel (15) is widened in the isotropic etching step, until the etching channel (15) is connected to the cavern.

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