Thin film resonators fabricated on membranes created by front side releasing
    171.
    发明公开
    Thin film resonators fabricated on membranes created by front side releasing 有权
    Herstellung vonDünnschichtresonatorendurchFreiätzungvon Oberseiten darunterliegender Membranen

    公开(公告)号:EP1180494A3

    公开(公告)日:2003-03-26

    申请号:EP01306284.9

    申请日:2001-07-20

    Abstract: A new bulk resonator may be fabricated by a process that is readily incorporated in the traditional fabrication techniques used in the fabrication of monolithic integrated circuits on a wafer. The resonator is decoupled from the wafer by a cavity etched under the resonator using selective etching through front openings (vias) in a resonator membrane. In a typical structure the resonator is formed over a silicon wafer by first forming a first electrode, coating a piezoelectric layer over both the electrode and the wafer surface and forming a second electrode opposite the first on the surface of the piezoelectric layer. After this structure is complete, a number of vias are etched in the piezoelectric layer exposing the surface under the piezoelectric layer to a selective etching process that selectively attacks the surface below the piezoelectric layer creating a cavity under the resonator.

    Abstract translation: 新的体谐振器可以通过容易地结合在晶片上制造单片集成电路中的传统制造技术中的工艺来制造。 谐振器通过在共振器下蚀刻的腔体与晶片分离,使用通过谐振器膜中的前开口(通孔)的选择性蚀刻。 在典型的结构中,谐振器通过首先形成第一电极而在硅晶片上形成,在电极和晶片表面上涂覆压电层,并形成与压电层表面上的第一电极相对的第二电极。 在该结构完成之后,在将压电层下方的表面暴露的压电层中蚀刻多个通孔到选择性蚀刻工艺,该选择性蚀刻工艺选择性地攻击压电层下方的表面,在谐振器下面形成空腔。

    CMOS-COMPATIBLE MEM SWITCHES AND METHOD OF MAKING
    172.
    发明公开
    CMOS-COMPATIBLE MEM SWITCHES AND METHOD OF MAKING 审中-公开
    CMOS兼容的微机电开关和方法及其

    公开(公告)号:EP1230660A2

    公开(公告)日:2002-08-14

    申请号:EP00959339.3

    申请日:2000-08-23

    Abstract: A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as viasto connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude towards each other. Thus, when the contacts are moved towards each other by actuating the MEM switch, they connect firmly without obstruction. Tungsten is typically used to form vias in CMOS processes, and it makes an excellent contact material, but other via metals may also be employed as contacts. Interconnect metallization may be employed for other structural and interconnect needs of the MEM switch, and is preferably standard for the foundry and process used. Various metals and dielectric materials may be used to create the switches, but in a preferred embodiment the interconnect metal layers are aluminum and the dielectric material is SiO2, materials which are fully compatible with standard four-layer CMOS fabrication processes.

    Etch control seal for dissolved wafer micromachining process
    173.
    发明公开
    Etch control seal for dissolved wafer micromachining process 失效
    密封在微加工方法的晶片的控制溶解。

    公开(公告)号:EP0678905A2

    公开(公告)日:1995-10-25

    申请号:EP95102347.2

    申请日:1995-02-20

    Inventor: Hays, Kenneth M.

    Abstract: A dissolved wafer micromachining process is modified by providing an etch control seal around the perimeter of a heavily doped micromechanical structure formed on a substrate. The micromechanical structure is fabricated on a wafer using conventional methods including the formation of a trench that surrounds and defines the shape of the micromechanical structure in the substrate. The etch control seal comprises a portion of the substrate in the form of a raised ring extending around the perimeter of the micromechanical structure and its defining trench. Selected raised areas of the heavily doped micromechanical structure and the top of the raised etch control seal are bonded to a second substrate. A selective etch is then used to dissolve the first substrate so that the heavily doped micromechanical structure remains attached to the second substrate only at the bonded areas. The etch control seal reduces exposure of the micromechanical structure and bonded areas to the etch by preventing the etch from contacting the heavily doped structure until the etch leaks through the dissolving floor of the trench. This occurs only during the final stages of the substrate dissolution step, thus minimizing exposure of the micromechanical structure and bonded areas to the damaging effects of the etch. Use of an etch control seal increases design flexibility and improves micromechanical device yield and quality in a dissolved wafer fabrication process.

    MICROSTRUCTURE AND METHOD OF MANUFACTURING THE SAME
    176.
    发明申请
    MICROSTRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    微结构及其制造方法

    公开(公告)号:WO2013187267A1

    公开(公告)日:2013-12-19

    申请号:PCT/JP2013/065301

    申请日:2013-05-27

    Inventor: KATO, Takahisa

    Abstract: Provided is a method of manufacturing a microstructure, including: a preparing step of preparing a silicon substrate having a first surface and a second surface; a first step of forming a hole in the first surface; a second step of forming, in the hole, a film formed of a material which has selectivity for an etchant to form an etching region, the region having side portions and a bottom portion surrounded by the film; a third step of forming, on the first surface, a first layer which is a multilayer film including an insulating layer and a metal layer stacked therein, at least one of the insulating layer and the metal layer being patterned, in a state where a position of the pattern and a position of the etching region are adjusted; a fourth step of forming a first opening which pierces the first layer; and a fifth step of introducing the etchant through the first opening to remove the etching region.

    Abstract translation: 提供一种制造微结构的方法,包括:准备具有第一表面和第二表面的硅衬底的制备步骤; 在第一表面形成孔的第一步骤; 在孔中形成由对腐蚀剂选择性形成蚀刻区域的材料形成的膜的第二步骤,所述区域具有侧部和由膜包围的底部; 第三步骤,在第一表面上形成第一层,其是包括绝缘层和堆叠在其中的金属层的多层膜,在绝缘层和金属层中的至少一个被图案化的状态下,在位置 并且调整蚀刻区域的位置; 形成穿透所述第一层的第一开口的第四步骤; 以及通过第一开口引入蚀刻剂以除去蚀刻区域的第五步骤。

    METHOD FOR MANUFACTURING A PROTECTIVE LAYER AGAINST HF ETCHING, SEMICONDUCTOR DEVICE PROVIDED WITH THE PROTECTIVE LAYER AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
    177.
    发明申请
    METHOD FOR MANUFACTURING A PROTECTIVE LAYER AGAINST HF ETCHING, SEMICONDUCTOR DEVICE PROVIDED WITH THE PROTECTIVE LAYER AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开
    用于制造抗蚀层的保护层的方法,用保护层提供的半导体器件及制造半导体器件的方法

    公开(公告)号:WO2013061313A8

    公开(公告)日:2013-08-01

    申请号:PCT/IB2012055982

    申请日:2012-10-29

    Abstract: A method for manufacturing a protective layer (25) for protecting an intermediate structural layer (22) against etching with hydrofluoric acid (HF), the intermediate structural layer (22) being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminium oxide, by atomic layer deposition, on the intermediate structural layer (22); performing a thermal crystallization process on the first layer of aluminium oxide, forming a first intermediate protective layer (25a),- forming a second layer of aluminium oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallisation process on the second layer of aluminium oxide, forming a second intermediate protective layer (25b) and thereby completing the formation of the protective layer (25). The method for forming the protective layer (25) can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.

    Abstract translation: 一种制造用于保护中间结构层(22)以防止用氢氟酸(HF)蚀刻的保护层(25)的方法,所述中间结构层(22)由可被氢氟酸蚀刻或损坏的材料制成, 该方法包括以下步骤:通过原子层沉积在中间结构层(22)上形成第一氧化铝层; 在第一氧化铝层上进行热结晶处理,形成第一中间保护层(25a), - 通过原子层沉积形成第二层氧化铝,在第一中间保护层上方; 以及对所述第二氧化铝层进行热结晶处理,形成第二中间保护层(25b),从而完成所述保护层(25)的形成。 形成保护层(25)的方法可以用于例如陀螺仪或加速度计等惯性传感器的制造步骤。

    MICROELECTRONIC COMPONENT
    178.
    发明申请
    MICROELECTRONIC COMPONENT 审中-公开
    MICRO电子元件

    公开(公告)号:WO2011128188A3

    公开(公告)日:2012-01-12

    申请号:PCT/EP2011054362

    申请日:2011-03-22

    CPC classification number: B81C1/00587 B81B2207/015 B81B2207/07 B81C2201/014

    Abstract: In a method for producing an MEMS component, wherein, in the course of producing the multilevel interconnect layer stack for connecting microelectronic circuits, micromechanical structure elements (7, 8, 9) that are to be exposed later are embedded at the same time, a cutout is subsequently produced from a substrate rear side (R) as far as the multilevel interconnect layer stack, and then the micromechanical structure elements in the multilevel interconnect layer stack are exposed through the cutout. In order to increase the process accuracy, as early as in the course of producing the multilevel interconnect layer stack or even in the front end of line, a reference mask (22) for defining a lateral position or a lateral extent of the micromechanical structure elements (7, 8, 9) to be exposed is produced, wherein the reference mask (22) is arranged on the substrate front side between the substrate and the multilevel interconnect layer stack or in a layer of the multilevel interconnect layer stack that is situated nearer to the substrate (1) in comparison with the structure element.

    Abstract translation: 被嵌入在一种用于制造MEMS装置,其中在生产所述多级Leitbahnschichtstapels的用于同时或随后连接微电子电路的过程中被暴露的微机械的结构元件(7,8,9),在基板背面侧的anschließendeine凹部(R)的 多级Leitbahnschichtstapel制备,然后通过在所述多级Leitbahnschichtstapel通过凹部微机械结构元件露出。 为了提高加工精度是已经在生产多级Leitbahnschichtstapels的过程中或甚至在线路的前端的基准掩模(22),以限定一个横向位置或侧向延伸derfreizulegenden微机械结构元件(7,8,9),使用参考掩模 (22)被设置在所述基板和所述多级Leitbahnschichtstapel之间或在与基板(1)更接近多级Leitbahnschichtstapels的层的结构元件的比较基板正面。

    圧力センサおよび圧力センサの製造方法
    179.
    发明申请
    圧力センサおよび圧力センサの製造方法 审中-公开
    压力传感器及制造压力传感器的方法

    公开(公告)号:WO2011148973A1

    公开(公告)日:2011-12-01

    申请号:PCT/JP2011/061970

    申请日:2011-05-25

    Abstract: 【課題】低コスト化かつ小型化を実現できる圧力センサを提供すること。 【解決手段】圧力センサ1は、内部に基準圧室8が形成されたシリコン基板2と、シリコン基板2の一部からなり、基準圧室8を区画するようにシリコン基板2の表層部に形成されたダイヤフラム10と、ダイヤフラム10において基準圧室8に臨む下表面に形成されたエッチングストップ層9とを含んでいる。ダイヤフラム10には、基準圧室8に連通した貫通孔11が形成され、貫通孔11内には、充填体13が配置されている。

    Abstract translation: 公开了一种低成本和小型压力传感器。 压力传感器(1)包括:具有内部形成的基准压力室(8)的硅基板(2) 隔膜(10),其由所述硅基板(2)的一部分构成,并且形成在所述硅基板(2)的所述表层部分中,使得所述参考压力室(8)被分隔; 以及形成在所述隔膜(10)的下表面上的所述下表面与所述基准压力室(8)相对的蚀刻停止层(9)。 在隔膜(10)中形成有与参考压力室(8)连通的通孔(11),并且在通孔(11)中设置有填料(13)。

    SILICON-RICH NITRIDE ETCH STOP LAYER FOR VAPOR HF ETCHING IN MEMS DEVICE FABRICATION
    180.
    发明申请
    SILICON-RICH NITRIDE ETCH STOP LAYER FOR VAPOR HF ETCHING IN MEMS DEVICE FABRICATION 审中-公开
    用于MEMS器件制造中的蒸汽高温蚀刻的富硅氮弧蚀刻层

    公开(公告)号:WO2010147839A2

    公开(公告)日:2010-12-23

    申请号:PCT/US2010038158

    申请日:2010-06-10

    Abstract: A thin silicon-rich nitride film (e.g., having a thickness in the range of around 100A to 10000A) deposited using low-pressure chemical vapor deposition (LPCVD) is used for etch stop during vapor HF etching in various MEMS wafer fabrication processes and devices. The LPCVD silicon-rich nitride film may replace, or be used in combination with, a LPCVD stoichiometric nitride layer in many existing MEMS fabrication processes and devices. The LPCVD silicon-rich nitride film is deposited at high temperatures (e.g., typically around 650-900 degrees C). Such a LPCVD silicon-rich nitride film generally has enhanced etch selectivity to vapor HF and other harsh chemical environments compared to stoichiometric silicon nitride and therefore a thinner layer typically can be used as an embedded etch stop layer in various MEMS wafer fabrication processes and devices and particularly for vapor HF etching processes, saving time and money in the fabrication process.

    Abstract translation: 使用低压化学气相沉积(LPCVD)沉积的薄的富硅氮化物膜(例如,厚度在约100A至10000A的范围内)用于各种MEMS晶片制造工艺和器件中的蒸气HF蚀刻期间的蚀刻停止 。 LPCVD富硅氮化物膜可以在许多现有的MEMS制造工艺和器件中替代或与其组合使用LPCVD化学计量氮化物层。 LPCVD富硅氮化物膜在高温(例如典型地约650-900℃)下沉积。 与化学计量的氮化硅相比,这种LPCVD富硅氮化物膜通常对蒸汽HF和其它苛刻的化学环境具有增强的蚀刻选择性,因此较薄的层通常可用作各种MEMS晶片制造工艺和器件中的嵌入式蚀刻停止层,以及 特别是对于蒸汽HF蚀刻工艺,节省了制造过程中的时间和金钱。

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