Abstract:
A new bulk resonator may be fabricated by a process that is readily incorporated in the traditional fabrication techniques used in the fabrication of monolithic integrated circuits on a wafer. The resonator is decoupled from the wafer by a cavity etched under the resonator using selective etching through front openings (vias) in a resonator membrane. In a typical structure the resonator is formed over a silicon wafer by first forming a first electrode, coating a piezoelectric layer over both the electrode and the wafer surface and forming a second electrode opposite the first on the surface of the piezoelectric layer. After this structure is complete, a number of vias are etched in the piezoelectric layer exposing the surface under the piezoelectric layer to a selective etching process that selectively attacks the surface below the piezoelectric layer creating a cavity under the resonator.
Abstract:
A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as viasto connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude towards each other. Thus, when the contacts are moved towards each other by actuating the MEM switch, they connect firmly without obstruction. Tungsten is typically used to form vias in CMOS processes, and it makes an excellent contact material, but other via metals may also be employed as contacts. Interconnect metallization may be employed for other structural and interconnect needs of the MEM switch, and is preferably standard for the foundry and process used. Various metals and dielectric materials may be used to create the switches, but in a preferred embodiment the interconnect metal layers are aluminum and the dielectric material is SiO2, materials which are fully compatible with standard four-layer CMOS fabrication processes.
Abstract:
A dissolved wafer micromachining process is modified by providing an etch control seal around the perimeter of a heavily doped micromechanical structure formed on a substrate. The micromechanical structure is fabricated on a wafer using conventional methods including the formation of a trench that surrounds and defines the shape of the micromechanical structure in the substrate. The etch control seal comprises a portion of the substrate in the form of a raised ring extending around the perimeter of the micromechanical structure and its defining trench. Selected raised areas of the heavily doped micromechanical structure and the top of the raised etch control seal are bonded to a second substrate. A selective etch is then used to dissolve the first substrate so that the heavily doped micromechanical structure remains attached to the second substrate only at the bonded areas. The etch control seal reduces exposure of the micromechanical structure and bonded areas to the etch by preventing the etch from contacting the heavily doped structure until the etch leaks through the dissolving floor of the trench. This occurs only during the final stages of the substrate dissolution step, thus minimizing exposure of the micromechanical structure and bonded areas to the damaging effects of the etch. Use of an etch control seal increases design flexibility and improves micromechanical device yield and quality in a dissolved wafer fabrication process.
Abstract:
The invention comprises a method for fabricating a monolithic chip containing integrated circuitry as well as a suspended polysilicon microstructure. The inventive method comprises 67 processes which are further broken down into approximately 330 steps. The processes and their arrangement allow for compatible fabrication of transistor circuitry and the suspended polysilicon microstructure on the same chip.
Abstract:
A Through Silicon Interposer Wafer and Method of Manufacturing the Same A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.
Abstract:
Provided is a method of manufacturing a microstructure, including: a preparing step of preparing a silicon substrate having a first surface and a second surface; a first step of forming a hole in the first surface; a second step of forming, in the hole, a film formed of a material which has selectivity for an etchant to form an etching region, the region having side portions and a bottom portion surrounded by the film; a third step of forming, on the first surface, a first layer which is a multilayer film including an insulating layer and a metal layer stacked therein, at least one of the insulating layer and the metal layer being patterned, in a state where a position of the pattern and a position of the etching region are adjusted; a fourth step of forming a first opening which pierces the first layer; and a fifth step of introducing the etchant through the first opening to remove the etching region.
Abstract:
A method for manufacturing a protective layer (25) for protecting an intermediate structural layer (22) against etching with hydrofluoric acid (HF), the intermediate structural layer (22) being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminium oxide, by atomic layer deposition, on the intermediate structural layer (22); performing a thermal crystallization process on the first layer of aluminium oxide, forming a first intermediate protective layer (25a),- forming a second layer of aluminium oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallisation process on the second layer of aluminium oxide, forming a second intermediate protective layer (25b) and thereby completing the formation of the protective layer (25). The method for forming the protective layer (25) can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.
Abstract:
In a method for producing an MEMS component, wherein, in the course of producing the multilevel interconnect layer stack for connecting microelectronic circuits, micromechanical structure elements (7, 8, 9) that are to be exposed later are embedded at the same time, a cutout is subsequently produced from a substrate rear side (R) as far as the multilevel interconnect layer stack, and then the micromechanical structure elements in the multilevel interconnect layer stack are exposed through the cutout. In order to increase the process accuracy, as early as in the course of producing the multilevel interconnect layer stack or even in the front end of line, a reference mask (22) for defining a lateral position or a lateral extent of the micromechanical structure elements (7, 8, 9) to be exposed is produced, wherein the reference mask (22) is arranged on the substrate front side between the substrate and the multilevel interconnect layer stack or in a layer of the multilevel interconnect layer stack that is situated nearer to the substrate (1) in comparison with the structure element.
Abstract:
A thin silicon-rich nitride film (e.g., having a thickness in the range of around 100A to 10000A) deposited using low-pressure chemical vapor deposition (LPCVD) is used for etch stop during vapor HF etching in various MEMS wafer fabrication processes and devices. The LPCVD silicon-rich nitride film may replace, or be used in combination with, a LPCVD stoichiometric nitride layer in many existing MEMS fabrication processes and devices. The LPCVD silicon-rich nitride film is deposited at high temperatures (e.g., typically around 650-900 degrees C). Such a LPCVD silicon-rich nitride film generally has enhanced etch selectivity to vapor HF and other harsh chemical environments compared to stoichiometric silicon nitride and therefore a thinner layer typically can be used as an embedded etch stop layer in various MEMS wafer fabrication processes and devices and particularly for vapor HF etching processes, saving time and money in the fabrication process.