公开(公告)号：US20090218119A1

公开(公告)日：2009-09-03

申请号：US12327444

申请日：2008-12-03

Applicant: Toru Nakai ,  Sho Akai

Inventor： Toru Nakai ,  Sho Akai

IPC: H05K1/00 ,  H05K1/09 ,  C25D5/02

CPC classification number: H05K3/4644 ,  H05K3/108 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/073 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165

Abstract: A method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film. The method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.

Abstract translation: 一种制造多层印刷线路板的方法包括在第一层间树脂绝缘层上形成第一层间树脂绝缘层，第一导体电路，第二层间树脂绝缘层，第二层间树脂绝缘层中的开口部分，露出面 第一导体电路的第二层间树脂绝缘层上的无电镀膜和暴露面，以及化学镀膜上的电镀抗蚀剂。 该方法还包括用具有比无电镀膜低的离子倾向的薄膜导体层和暴露面的金属代替化学镀膜，在化学镀膜的一部分上形成包括金属的电镀膜 和薄膜导体层，剥离电镀抗蚀剂，以及除去通过剥离暴露的化学镀膜。

公开(公告)号：US20090020322A1

公开(公告)日：2009-01-22

申请号：US12175348

申请日：2008-07-17

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K1/18

CPC classification number: H05K3/3473 ,  H01L23/498 ,  H01L23/49816 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13565 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/099 ,  H05K2203/054 ,  H01L2224/05552

Abstract: A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Abstract translation: 提供一种具有导电结构的封装基板，包括：具有在其表面上至少有一个导电焊盘的基板主体，设置在导电焊盘上的应力缓冲金属层，设置在基板主体上的阻焊层，并具有至少一个开口 用于相应地暴露应力缓冲金属层的顶表面的一部分，设置在应力缓冲金属层的表面的中心部分上的金属柱和覆盖金属柱的表面的焊料凸块。 因此，通过使用应力缓冲金属层来释放热应力，并且使用金属柱和焊料凸块来增加导电结构的高度，提供了高度可靠的导电结构。

公开(公告)号：US20070158852A1

公开(公告)日：2007-07-12

申请号：US11467296

申请日：2006-08-25

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K3/421 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/09563 ,  H01L2924/00

Abstract: A method for fabricating a circuit board with a conductive structure and the same are proposed. A buffer metal layer is formed on an electrically connecting pad of a circuit layer of a circuit board in advance. A conductive structure is then formed on the buffer metal layer to form the conductive structure of the present invention and is connected to the circuits located in the different layers of the circuit board. The combining strength of the conductive structure and the electrically connecting pad is reinforced by the buffer metal layer as the buffer metal layer has high ductility. The long-term electrical quality and stability are also enhanced.

Abstract translation: 提出了一种制造具有导电结构的电路板的方法。 预先在电路板的电路层的电连接焊盘上形成缓冲金属层。 然后在缓冲金属层上形成导电结构以形成本发明的导电结构，并连接到位于电路板不同层中的电路。 当缓冲金属层具有高延展性时，导电结构和电连接焊盘的组合强度被缓冲金属层增强。 长期的电气质量和稳定性也得到提高。

公开(公告)号：US4572925A

公开(公告)日：1986-02-25

申请号：US589025

申请日：1984-03-13

Applicant: John A. Scarlett

Inventor： John A. Scarlett

IPC: H05K3/06 ,  H05K3/24 ,  H05K3/34 ,  H05K3/42 ,  H05K1/09

CPC classification number: H05K3/244 ,  H05K3/062 ,  H05K2201/0341 ,  H05K2201/09736 ,  H05K2203/0571 ,  H05K2203/072 ,  H05K3/243 ,  H05K3/3473 ,  H05K3/427 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Printed circuit manufacture may employ a plated palladium-nickel alloy layer as an etch resist and plating finish. Prior to the use of palladium-nickel, tin-lead was used as the etch resist and plating finish. The palladium-nickel layer is generally superior to the corresponding tin-lead layer except for solderability. To improve the solderability of at least these areas of the palladium-nickel to which elements are to be soldered, a layer of copper is deposited thereon. If desired, the solderability of the copper may be preserved by coating it with, for example, a tin-lead layer.

Abstract translation: 印刷电路制造可以使用电镀钯 - 镍合金层作为抗蚀剂和电镀。 在使用钯镍之前，使用锡铅作为抗蚀剂和镀层。 除了可焊性之外，钯 - 镍层通常优于相应的锡 - 铅层。 为了提高至少这些要被焊接元件的钯 - 镍的这些区域的可焊性，在其上沉积一层铜。 如果需要，铜的可焊性可以通过用例如锡 - 铅层涂覆来保护。

公开(公告)号：US20240292523A1

公开(公告)日：2024-08-29

申请号：US18571937

申请日：2022-06-15

Applicant: CORNING INCORPORATED

Inventor： JOON-SOO KIM ,  YOUNG SUK LEE ,  BYUNGDOO MOON ,  HYUNG SOO MOON

IPC: H05K1/02 ,  C03C17/09 ,  C03C17/10 ,  C03C17/36 ,  C23C14/18 ,  C23C18/38 ,  C23C28/02 ,  H05K1/09 ,  H05K3/18

CPC classification number: H05K1/0271 ,  C03C17/09 ,  C03C17/10 ,  C03C17/3639 ,  C03C17/3649 ,  C23C14/185 ,  C23C18/38 ,  C23C28/023 ,  H05K1/09 ,  C03C2218/111 ,  C03C2218/154 ,  H05K3/181 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2203/072

Abstract: A layered structure, an article such as circuit board including such a layered structure, and methods of making the same are provided. The layered structure includes a substrate comprising glass or glass ceramic, an adhesion layer disposed on the substrate, a seed layer disposed on the adhesion layer, a first conductive layer disposed on the seed layer, and a second conductive layer disposed on the first conductive layer. The seed layer includes a first metal material and has a first type of stress with respect to the substrate. The first conductive layer includes the first metal material and has a second type of stress with respect to the substrate. The second conductive layer includes a second metal material and has the first type of stress with respect to the substrate. The layered structure may further include additional pairs of alternating layers of the first and the second conductive layers.

公开(公告)号：US09940957B2

公开(公告)日：2018-04-10

申请号：US15223241

申请日：2016-07-29

Applicant: Nitto Denko Corporation

Inventor： Daisuke Yamauchi ,  Hiroyuki Tanabe

IPC: H05K1/09 ,  H05K1/05 ,  G11B5/48 ,  H05K1/11 ,  H05K3/24 ,  H05K3/38

CPC classification number: G11B5/4833 ,  G11B5/484 ,  H05K1/056 ,  H05K1/09 ,  H05K1/111 ,  H05K3/244 ,  H05K3/388 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/05 ,  Y02P70/611

Abstract: A conductor trace is formed on a base insulating layer. The conductor trace includes two terminal portions and one wiring portion. The wiring portion is formed to connect the two terminal portions to each other and extend from each terminal portion. A metal cover layer is formed to cover the terminal portion and the wiring portion of the conductor trace and continuously extend from a surface of the terminal portion to a surface of the wiring portion. The metal cover layer is made of metal having magnetism lower than magnetism of nickel, and is made of gold, for example. A cover insulating layer is formed on the base insulating layer to cover a portion, of the metal cover layer formed on the conductor trace, covering the wiring portion and not to cover a portion of the metal cover layer covering the terminal portion.

公开(公告)号：US20180004318A1

公开(公告)日：2018-01-04

申请号：US15200949

申请日：2016-07-01

Applicant: Khaled Ahmed ,  Prashant Majhi

Inventor： Khaled Ahmed ,  Prashant Majhi

IPC: G06F3/041 ,  C23C14/34 ,  H05K1/09 ,  C23C16/50 ,  C23C14/14 ,  H05K1/02 ,  H01J37/32 ,  C23C16/24

CPC classification number: G06F3/041 ,  G06F2203/04102 ,  G06F2203/04103 ,  H01J37/32009 ,  H01J37/32532 ,  H01J2237/3321 ,  H01J2237/334 ,  H05K1/0271 ,  H05K1/0346 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/0014 ,  H05K3/007 ,  H05K3/027 ,  H05K3/067 ,  H05K3/107 ,  H05K2201/0154 ,  H05K2201/0323 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0385 ,  H05K2201/0391 ,  H05K2203/0759 ,  H05K2203/0769 ,  H05K2203/107

Abstract: Systems, apparatuses, and/or methods to manufacture and/or implement a sensor film, a composite electrode, and/or a computing device such as a flexible device. The sensor film may include a random network of metal lines and graphene interconnecting the metal lines. The composite electrode may be formed from the sensor film. In addition, the composite electrode may include a first portion including a metal layer in a graphene layer, wherein the metal layer is randomly located in the graphene layer, and a second portion excluding the metal layer and including the graphene layer. The sensor film may be patterned to include any composite electrode configuration, such as an antenna electrode configuration, a touch electrode configuration, and so on. Thus, the flexible device may include a flexible touch screen.

公开(公告)号：US09847308B2

公开(公告)日：2017-12-19

申请号：US14566185

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan ,  Ravindranath V. Mahajan

IPC: H01L23/00 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/1132 ,  H01L2224/11418 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/13316 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13387 ,  H01L2224/13411 ,  H01L2224/13447 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/75264 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81222 ,  H01L2224/81409 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/3494 ,  H05K2201/0341 ,  H05K2201/083 ,  H05K2201/10674 ,  H05K2203/104 ,  Y02P70/613 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05381 ,  H01L2924/053 ,  H01L2924/0532 ,  H01L2924/01056

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.

公开(公告)号：US20170301647A1

公开(公告)日：2017-10-19

申请号：US15593176

申请日：2017-05-11

Applicant: Skyworks Solutions, Inc.

Inventor： Sandra Louise Petty-Weeks ,  Guohao Zhang ,  Hardik Bhupendra Modi

IPC: H01L23/00 ,  H01L23/66 ,  H05K1/02 ,  H05K3/24

CPC classification number: H01L24/85 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48844 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1421 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K3/244 ,  H05K2201/0341 ,  H01L2924/00014 ,  H01L2924/00

Abstract: This disclosure relates to a radio frequency (RF) transmission line for high performance RF applications. The RF transmission line includes a conductive layer and finish plating on the conductive layer. The finish plating includes a gold layer, a palladium layer proximate the gold layer, and a nickel layer proximate the palladium layer. The nickel layer has a thickness that allows a radio frequency signal received at the gold layer to penetrate the nickel layer and propagate in the conductive layer.

公开(公告)号：US09576693B2

公开(公告)日：2017-02-21

申请号：US14346025

申请日：2012-09-10

Applicant: Yoshitaka Shibuya ,  Kazuhiko Fukamachi ,  Atsushi Kodama

Inventor： Yoshitaka Shibuya ,  Kazuhiko Fukamachi ,  Atsushi Kodama

IPC: B32B15/00 ,  H01B1/02 ,  B32B15/01 ,  C25D5/10 ,  C22C5/06 ,  C22C5/08 ,  C22C5/10 ,  C22C9/00 ,  C22C9/02 ,  C22C9/04 ,  C22C13/00 ,  C22C19/03 ,  C22C19/07 ,  C22C22/00 ,  C22C27/06 ,  C22C38/00 ,  C22C13/02 ,  H05K3/24 ,  C25D5/50 ,  C25D5/12 ,  C23C18/16 ,  H05K1/11 ,  H01R13/03 ,  C25D3/12 ,  C25D3/20 ,  C25D3/30 ,  C25D3/38 ,  C25D3/46 ,  C25D3/50 ,  C25D3/56 ,  C25D3/62 ,  C25D3/64

CPC classification number: H01B1/02 ,  B32B15/01 ,  B32B15/018 ,  C22C5/06 ,  C22C5/08 ,  C22C5/10 ,  C22C9/00 ,  C22C9/02 ,  C22C9/04 ,  C22C13/00 ,  C22C13/02 ,  C22C19/03 ,  C22C19/07 ,  C22C22/00 ,  C22C27/06 ,  C22C38/00 ,  C23C18/1651 ,  C23C18/1692 ,  C25D3/12 ,  C25D3/20 ,  C25D3/30 ,  C25D3/38 ,  C25D3/46 ,  C25D3/50 ,  C25D3/567 ,  C25D3/62 ,  C25D3/64 ,  C25D5/10 ,  C25D5/12 ,  C25D5/505 ,  H01R13/03 ,  H05K1/117 ,  H05K1/118 ,  H05K3/244 ,  H05K2201/0341 ,  Y10T428/12681 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12722

Abstract: There are provided a metal material for electronic component which has low insertability/extractability, low whisker formability, and high durability, and a method for manufacturing the metal material. The metal material 10 for electronic components has a base material 11, an A layer 14 constituting a surface layer on the base material 11 and formed of Sn, In or an alloy thereof, and a B layer 13 constituting a middle layer provided between the base material 11 and the A layer 14 and formed of Ag, Au, Pt, Pd, Ru, Rh, Os, Ir or an alloy thereof, wherein the surface layer (A layer) 14 has a thickness of 0.002 to 0.2 μm, and the middle layer (B layer) 13 has a thickness of 0.001 to 0.3 μm.

Abstract translation: 提供了具有低插入性/提取性，低晶须成形性和高耐久性的电子部件用金属材料以及金属材料的制造方法。 用于电子部件的金属材料10具有基材11，构成基材11的表层的A层14，其由Sn，In或其合金形成，B层13构成中间层， 材料11和A层14，由Ag，Au，Pt，Pd，Ru，Rh，Os，Ir或其合金形成，其中表面层（A层）14的厚度为0.002〜0.2μm， 中间层（B层）13的厚度为0.001〜0.3μm。