公开(公告)号：US11877728B2

公开(公告)日：2024-01-23

申请号：US17494911

申请日：2021-10-06

Applicant: CANON KABUSHIKI KAISHA

Inventor： Takahiro Furuya ,  Takatoshi Kamei ,  Tsutomu Inaba ,  Bin Qi ,  Kei Tashiro ,  Yoshihiro Egashira

IPC: A61B1/05 ,  H05K1/02 ,  H05K1/11 ,  H04N23/50 ,  A61B1/00

CPC classification number: A61B1/051 ,  H04N23/50 ,  H05K1/028 ,  H05K1/118 ,  A61B1/00105 ,  H04N23/555 ,  H05K2201/09027 ,  H05K2201/0939 ,  H05K2201/09445

Abstract: An imaging module includes an electric cable including a plurality of wirings, an imager having an imaging surface intersecting an axial direction of a distal end of the electric cable, and a flexible wiring board configured to electrically connect the imager and the electric cable. The wiring board includes a plurality of extending portions that extend from at least three portions of a connection portion connected with the imager. At least one wiring pad to which at least one of the plurality of wirings of the electric cable is connected is provided in each of the plurality of extending portions.

公开(公告)号：US20230328873A1

公开(公告)日：2023-10-12

申请号：US17715673

申请日：2022-04-07

Applicant: Western Digital Technologies, Inc.

Inventor： Lin Hui Chen ,  Songtao Lu ,  Chien Te Chen ,  Yu Ying Tan ,  Huang Pao Yi ,  Ching Chuan Hsieh ,  T. Sharanya Kaminda ,  Chia-Hsuan Huang

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0218 ,  H05K1/116 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

公开(公告)号：US11751333B2

公开(公告)日：2023-09-05

申请号：US17476625

申请日：2021-09-16

Applicant: Google LLC

Inventor： John Martinis ,  Bob Benjamin Buckley ,  Xiaojun Trent Huang

IPC: H05K1/14 ,  H05K1/11 ,  H05K1/02 ,  H05K3/36

CPC classification number: H05K1/144 ,  H05K1/028 ,  H05K1/115 ,  H05K1/118 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/0939 ,  H05K2201/09481

Abstract: An interconnection for flex circuit boards used, for instance, in a quantum computing system are provided. In one example, the interconnection can include a first flex circuit board having a first side and a second side opposite the first side. The interconnection can include a second flex circuit board having a third side and a fourth side opposite the third side. The first flex circuit board and the second flex circuit board are physically coupled together in an overlap joint in which a portion of the second side for the first flex circuit board overlaps a portion of the third side of the flex circuit board. The interconnection can include a signal pad structure positioned in the overlap joint that electrically couples a first via in the first flex circuit board and a second via in the second flex circuit board.

公开(公告)号：US11696399B2

公开(公告)日：2023-07-04

申请号：US17635916

申请日：2020-09-15

Applicant: ZTE Corporation

Inventor： Changgang Yin ,  Bi Yi ,  Zhongmin Wei

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K1/115 ,  H05K2201/0939 ,  H05K2201/09481 ,  H05K2201/09854

Abstract: A circuit board is disclosed, including a circuit board body and at least one via apparatus provided on the circuit board body. The via apparatus includes a via (101) formed on the circuit board body, a via pad (201) surrounding the via and separately provided from the via, and an electrical conductor (301) electrically connecting the via pad (201) with the via (101).

公开(公告)号：US11690174B2

公开(公告)日：2023-06-27

申请号：US17273593

申请日：2020-06-05

Applicant: Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ren Xiong ,  Fan Li ,  Qiang Tang ,  Fei Shang ,  Haijun Qiu ,  Yuanyuan Chai ,  Huiqiang Song

IPC: H05K1/11 ,  G06F3/044 ,  G06F3/041 ,  H01R12/61 ,  H05K3/36 ,  H05K1/18 ,  H10K59/131 ,  H10K59/179

CPC classification number: H05K1/118 ,  G06F3/0412 ,  G06F3/0443 ,  G06F3/0446 ,  H01R12/61 ,  H05K3/363 ,  G06F3/04164 ,  H05K1/189 ,  H05K2201/041 ,  H05K2201/0939 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09481 ,  H05K2201/10128 ,  H10K59/131 ,  H10K59/179

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a display panel and a flexible circuit board electrically connected with the display panel. The flexible circuit board includes a first circuit board, a second circuit board and a conductive portion; the first circuit board includes a first substrate, and a main contact pad, a first wire and a second wire provided on the first substrate; the second circuit board includes a second substrate, a relay contact pad and a third wire provided on the second substrate; and the conductive portion is configured for electrically connecting the main contact pad and the relay contact pad.

公开(公告)号：US20230171882A1

公开(公告)日：2023-06-01

申请号：US17921778

申请日：2021-04-26

Applicant: LG INNOTEK CO., LTD.

Inventor： Hae Sik KIM ,  Jee Heum PAIK

IPC: H05K1/02 ,  H05K1/11 ,  H04N23/68

CPC classification number: H05K1/0296 ,  H04N23/687 ,  H05K1/116 ,  H05K2201/0939 ,  H05K2201/09618 ,  H05K2201/10151 ,  H05K2201/10287

Abstract: A circuit board according to an embodiment includes an insulating layer; and a lead pattern portion disposed on the insulating layer, wherein the lead pattern portion includes: a first portion disposed on the insulating layer; and a second portion extending from one end of the first portion; wherein the first portion is disposed overlapping the insulating layer in a vertical direction, wherein the second portion is disposed in an outer region of the insulating layer and does not overlap the insulating layer; and wherein the lead pattern portion has a centerline average roughness in a range of 0.05 µm to 0.5 µm or a 10-point average roughness in a range of 1.0 µm to 5.0 µm.

公开(公告)号：US09831144B2

公开(公告)日：2017-11-28

申请号：US14428376

申请日：2013-08-28

Applicant: QUBEICON LTD.

Inventor： Shimon Podval

IPC: H05K1/18 ,  H01L23/13 ,  H01L23/498 ,  H01L25/065 ,  H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H01L23/00 ,  H05K3/34

CPC classification number: H01L23/13 ,  H01L23/49838 ,  H01L23/49855 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/15162 ,  H01L2924/15192 ,  H05K1/0204 ,  H05K1/117 ,  H05K1/141 ,  H05K3/3415 ,  H05K3/3442 ,  H05K2201/041 ,  H05K2201/09063 ,  H05K2201/09154 ,  H05K2201/09163 ,  H05K2201/0939 ,  H05K2201/09472 ,  Y02P70/613 ,  H01L2924/014 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and having relatively narrow edge surfaces and first and second relatively large face surfaces; at least one recess formed along an edge surface; a layer of a conducting material formed on a surface of each of the at least one recess; a first plurality of soldering pads on the first face surface configured to make electrical contact with a semiconductor device; and electrically conducting connections each of which electrically connects a soldering pad in the first plurality of soldering pads to the layer of conducting material of a recess of the at least one recess.

公开(公告)号：US20170336584A1

公开(公告)日：2017-11-23

申请号：US15673484

申请日：2017-08-10

Applicant: FURUKAWA ELECTRIC CO., LTD.

Inventor： Maiko ARIGA ,  Etsuji KATAYAMA ,  Toshio SUGAYA

IPC: G02B6/42 ,  H05K1/11 ,  H05K1/02 ,  G02B6/27 ,  H01S5/0683 ,  H01S5/06

CPC classification number: G02B6/4281 ,  G02B6/2706 ,  G02B6/4246 ,  H01S5/0612 ,  H01S5/06837 ,  H05K1/028 ,  H05K1/115 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3447 ,  H05K2201/0939 ,  H05K2201/09409 ,  H05K2201/10121

Abstract: A flexible substrate includes: an insulating base member; a plurality of lands formed aligned in a plurality of lines in a first direction on the base member; and a plurality of wirings formed on the base member, extending in a second direction intersecting the first direction, and connected to the plurality of lands on each line of the plurality of lines, wherein the plurality of wirings include a wiring extending between the lands aligned in the first direction, and wherein each of the plurality of lands has a planar shape longer in the second direction.

公开(公告)号：US09773761B2

公开(公告)日：2017-09-26

申请号：US14903858

申请日：2014-07-08

Applicant: PSI CO., LTD.

Inventor： Young Rag Do

IPC: H01L33/62 ,  H01L25/075 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H01L33/38

CPC classification number: H01L25/0753 ,  H01L33/38 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0066 ,  H05K1/0295 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09427 ,  H05K2201/09954 ,  H05K2201/10106 ,  H05K2201/10583 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2203/048 ,  Y02P70/611 ,  H01L2924/00

Abstract: Provided are a nano-scale LED assembly and a method for manufacturing the same. First, a nano-scale LED device that is independently manufactured may be aligned and connected to two electrodes different from each other to solve a limitation in which a nano-scale LED device having a nano unit is coupled to two electrodes different from each other in a stand-up state. Also, since the LED device and the electrodes are disposed on the same plane, light extraction efficiency of the LED device may be improved. Furthermore, the number of nano-scale LED devices may be adjusted. Second, since the nano-scale LED device does not stand up to be three-dimensionally coupled to upper and lower electrodes, but lies to be coupled to two electrodes different from each other on the same plane, the light extraction efficiency may be very improved. Also, since a separate layer is formed on a surface of the LED device to prevent the LED device and the electrode from being electrically short-circuited, defects of the LED electrode assembly may be minimized. Also, in preparation for the occurrence of the very rare defects of the LED device, the plurality of LED devices may be connected to the electrode to maintain the original function of the nano-scale LED electrode assembly.

公开(公告)号：US09577304B2

公开(公告)日：2017-02-21

申请号：US14637898

申请日：2015-03-04

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： Chih-Heng Chuo ,  Gwun-Jin Lin ,  Kuo-Fu Su

IPC: H03H7/38 ,  H01P1/22 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01P1/227 ,  H03H7/38 ,  H05K1/0225 ,  H05K1/0251 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3447 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09718 ,  H05K2201/10931

Abstract: Disclosed is an attenuation reduction structure for high-frequency connection pads of a circuit board with an insertion component. The circuit board includes at least one pair of differential mode signal lines formed thereon. A substrate has upper and lower surfaces respectively provided with at least one pair of upper connection pads and lower connection pads. A first metal layer is formed on the lower surface of the substrate. The first metal layer includes an attenuation reduction grounding pattern structure. The attenuation reduction grounding pattern structure includes a hollow area and at least one protruded portion. The protruded portion extends from the first metal layer in a direction toward the lower connection pads.

Abstract translation: 公开了一种具有插入部件的电路板的高频连接焊盘的衰减减小结构。 电路板包括形成在其上的至少一对差模信号线。 衬底具有分别设置有至少一对上连接焊盘和下连接焊盘的上表面和下表面。 第一金属层形成在基板的下表面上。 第一金属层包括衰减减小接地图案结构。 衰减降低接地图案结构包括中空区域和至少一个突出部分。 突出部分沿着朝向下连接焊盘的方向从第一金属层延伸。