USB 2.0 대역폭 예약을 위한 방법 및 시스템
    11.
    发明公开
    USB 2.0 대역폭 예약을 위한 방법 및 시스템 审中-公开
    USB 2.0带宽预留的方法和系统

    公开(公告)号:KR20180030985A

    公开(公告)日:2018-03-27

    申请号:KR20187001689

    申请日:2016-07-22

    CPC classification number: G06F13/385 G06F13/1673 G06F13/4282 H04L67/322

    Abstract: USB 허브에대역폭을예약하기위한시스템들과방법들이개시된다. 상기시스템들과방법들은, 적어도하나의다운스트림엔드포인트로부터버퍼내의데이터를수신하는것, 상기버퍼의현재용량을식별하는것, 상기버퍼의상기현재용량을버퍼임계값과비교하는것, 적어도상기비교에근거하여출력값을발생시키는것, 적어도상기출력값에근거하여, 적어도하나의저-처리량엔드포인트를동적으로스로틀하는것, 및상기적어도하나의저-처리량엔드포인트들의스로틀로부터이용가능한 USB 디바이스에대역폭을제공함으로써, 미리결정된대역폭요구사항을갖는상기 USB 디바이스에미리정의된대역폭을할당하는것을포함할수 있다.

    Abstract translation: 公开了用于在USB集线器上预留带宽的系统和方法。 该系统和方法可以包括:从至少一个下游端点接收缓冲器中的数据,识别缓冲器的当前容量,将缓冲器的当前容量与缓冲器阈值进行比较, 至少基于输出值动态地抑制至少一个低吞吐量端点,并且从至少一个低吞吐量端点的节流器向可用USB设备提供带宽 并且将预定义的带宽分配给具有预定带宽要求的USB设备。

    한정된 메모리 어드레싱을 구비한 기존의 마이크로프로세서 아키텍처에서 데이터 메모리를 확장하기 위한 방법
    12.
    发明公开
    한정된 메모리 어드레싱을 구비한 기존의 마이크로프로세서 아키텍처에서 데이터 메모리를 확장하기 위한 방법 审中-公开
    用有限的存储器寻址扩展现有微处理器体系结构中数据存储器的方法

    公开(公告)号:KR20180030028A

    公开(公告)日:2018-03-21

    申请号:KR20187000742

    申请日:2016-07-14

    Abstract: 복수의메모리뱅크들로분할된데이터메모리에액세스하기위해뱅크선택액세스체계를사용하는마이크로프로세서아키텍처용데이터메모리를확장하는방법이개시된다. 뱅크선택레지스터는메모리뱅크를선택하도록구성되며, 마이크로프로세서아키텍처는메모리뱅크를선택하기위한전용명령어를갖는명령어세트를갖는다. 전용뱅크선택명령어의명령코드는최대 n개비트들의페이로드를제공하고, 이에의해최대 2n개의메모리뱅크들을선택하도록구성된어드레스값을제공한다. 이방법은: 새로운뱅크선택명령어를위해 m개비트들의페이로드를제공하는테스트명령어의명령코드를사용하는단계(여기서 m>n임); 그리고새로운테스트명령어를위해상기전용뱅크선택명령어의명령코드를사용하는단계를포함한다.

    Abstract translation: 公开了一种用于使用存储体选择访问方案来扩展用于微处理器体系结构的数据存储器以访问被划分成多个存储体的数据存储器的方法。 存储体选择寄存器被配置为选择存储体,并且微处理器体系结构具有一组具有用于选择存储体的专用指令的指令。 专用存储体选择指令的指令代码提供高达n位的有效载荷,由此提供被配置为选择高达2n个存储体的地址值。 使用提供m位有效载荷的测试指令的指令代码用于新的存储体选择指令(其中m> n); 并使用专用银行选择指令的指令代码用于新的测试指令。

    크리스털 발진기용 주기적인 킥스타터
    13.
    发明公开
    크리스털 발진기용 주기적인 킥스타터 审中-公开
    晶体振荡器的定期kickstarter

    公开(公告)号:KR20180020211A

    公开(公告)日:2018-02-27

    申请号:KR20187000746

    申请日:2016-06-21

    Inventor: KUMAR AJAY

    Abstract: 발진기의크리스털공진주파수에가까운펄스반복속도를갖는주기적인펄싱발진기는크리스털발진기회로에보다유용한시동에너지를제공하며, 따라서훨씬더 빠른시동시간을제공한다. 시동펄싱발진기는여러사이클들동안또는크리스털발진기진폭이소망값으로증가할때까지실행된다. 상기펄싱발진기는크리스털공진주파수의약 1/3 내지약 1/2의반복속도를가질수 있고, 따라서보다유용한시동에너지를크리스털발진기회로에제공할수 있다.

    Abstract translation: 脉冲重复率接近振荡器的晶体谐振频率的周期性脉冲振荡器为晶体振荡器电路提供更有用的启动能量,从而提供更快的启动时间。 启动脉冲振荡器运行几个周期或直到晶体振荡器振幅增加到所需值。 脉冲振荡器可以具有晶体谐振频率的约1/3至约1/2的重复频率,从而为晶体振荡器电路提供更有用的启动能量。

    라인 동작 검출기를 구비한 UART
    14.
    发明公开
    라인 동작 검출기를 구비한 UART 审中-公开
    带有线路运动检测器的UART

    公开(公告)号:KR20180020164A

    公开(公告)日:2018-02-27

    申请号:KR20177036680

    申请日:2016-06-22

    Inventor: SAMUEL ROSHAN

    CPC classification number: H04L27/2647 G06F13/4295 H04B1/16 H04L25/069

    Abstract: 범용비동기식수신기/송신기(UART) 모듈이개시된다. UART 모듈은 UART 모듈의데이터라인과결합되는에지검출기를포함할수 있고, 여기서에지검출기는상승및 하강에지에서카운터를리셋한다.

    Abstract translation: 公开了一种通用异步收发器(UART)模块。 UART模块可以包括耦合到UART模块的数据线的边沿检测器,其中边沿检测器在上升沿和下降沿重置计数器。

    내부 타이머를 구비한 아날로그-디지털 컨버터
    15.
    发明公开
    내부 타이머를 구비한 아날로그-디지털 컨버터 审中-公开
    具有内部定时器的模数转换器

    公开(公告)号:KR20180006905A

    公开(公告)日:2018-01-19

    申请号:KR20177032351

    申请日:2016-05-06

    Abstract: 아날로그-디지털컨버터는: 아날로그입력을수신하고상기입력을디지털신호로변환하기위한회로망; 및비-일시적제어회로망을포함하고, 상기비-일시적제어회로망은: 샘플링시간을수신하고; 변환시간을수신하고; 적어도하나의슬립모드로부터파워업 시간을결정하고; 그리고상기파워업 시간및 변환시간의합계가상기샘플링시간보다작으면, 상기디지털-아날로그컨버터를상기적어도하나의슬립모드로진입시키도록구성된다.

    Abstract translation: 该模数转换器包括:用于接收模拟输入并将输入转换为数字信号的电路; 以及非暂时性控制网络,其中所述非暂时性控制网络包括:接收采样时间; 接收转换时间; 从至少一个睡眠模式确定加电时间; 并且如果加电时间和转换时间之和小于采样时间,则将数模转换器输入至少一个睡眠模式。

    STRESS REDUCTION FOR LEAD FRAME DURING PLASTIC SEALING

    公开(公告)号:JP2001284516A

    公开(公告)日:2001-10-12

    申请号:JP2001073168

    申请日:2001-03-14

    Abstract: PROBLEM TO BE SOLVED: To obtain a lead frame equipping structure in which a contact region between the lead frame mounting structure and an integrated circuit die and to obtain a designing method in which a stress generated by thermal expansion can be dispersed to a bigger region than the die between points with which the lead frame is contacted. SOLUTION: This method in which an integrated circuit die is mounted in a mounting structure contains a step of forming the mounting structure having a die pad and a spreader at least, a step of mounting a contact part on the die pad of the mounting structure and the one spreader at least and a step of the one spreader at least existing between the die pad and the integrated circuit die.

    COLLISION DETECTION FOR DUAL PORT RAM OPERATION OF MICROCONTROLLER

    公开(公告)号:JP2001229072A

    公开(公告)日:2001-08-24

    申请号:JP2001013888

    申请日:2001-01-22

    Abstract: PROBLEM TO BE SOLVED: To provide a memory storage architecture for preventing the generation of any time delay to arbitrary writing access in a memory. SOLUTION: This device is provided with a dual port device, a first device including an interrupting input, a first data bus, and a first address bus operationally connected to the dual port device, a second device including a second data bus and a second address bus operationally connected to the dual port device, and an address comparator operationally connected to the first address bus and the second address bus for generating a collision error signal according to a prescribed simultaneous access from the first and second devices to the dual device.

    LOW POWER DIGITAL INPUT CIRCUIT
    18.
    发明专利

    公开(公告)号:JP2000134085A

    公开(公告)日:2000-05-12

    申请号:JP26117899

    申请日:1999-09-14

    Abstract: PROBLEM TO BE SOLVED: To obtain an input circuit that reduces a power consumption rate of a digital circuit connecting to the input circuit. SOLUTION: An input buffer 10 minimizes a power consumption rate of a device connecting to the input buffer 10, and the input buffer 10 is provided with a combination of a current source 14 that limits a current within a cross conduction range and a saturation amplifier 12 that connects to the current source 14 and has an input gain substantially higher than the unity to increase a speed of a transmission function.

    COMBINED INDUCTION COIL IN SINGLE LEAD FRAME PACKAGE, INTEGRATED CIRCUIT SEMICONDUCTOR CHIP, AND COMBINING METHOD

    公开(公告)号:JP2000124388A

    公开(公告)日:2000-04-28

    申请号:JP33880099

    申请日:1999-11-29

    Abstract: PROBLEM TO BE SOLVED: To function an induction coil as an antenna of a chip by a method wherein a lead frame having a coil structure and an integrated circuit semiconductor chip are combined within a single lead frame package, and the chip is electrically connected to a part of the coil structure of the lead frame. SOLUTION: A package 10 contains a plastic sealing envelope 12, and a lead frame structure 14 of an induction coil shape/structure is housed in the plastic sealing envelope 12. Two terminal pads 26, 28 of an integrated circuit semiconductor chip 24 are connected to an outside end part 30 and an inside end part 32 of an induction coil 14 via conductive wire bonds 34, 36. When the chip 24 is a transmitter type integrated circuit semiconductor chip, generated electric signals are transmitted to the induction coil 14 functioning as a transmission antenna. Furthermore, when the chip 24 is a receiver type integrated circuit semiconductor chip, electric signals are received by the induction coil 14 functioning as a reception antenna.

    GENERAL USE PROGRAMMING COIL PROGRAMMING TAG COIL OF VARIOUS CONSTITUTIONS

    公开(公告)号:JP2000047713A

    公开(公告)日:2000-02-18

    申请号:JP347999

    申请日:1999-01-08

    Inventor: YOUBOK LEE

    Abstract: PROBLEM TO BE SOLVED: To obtain an improved programming coil by making the coil include mutually coupled plural programming coils generating signals for coupling a general use programmer with tag coils of various constitutions so as to program the tag coils. SOLUTION: The tag coil 12 of a radio frequency identification(RFID) device 10 is provided nearby a programming coil 14. A programming unit 16 sends a signal to the programming coil 14. The programming coil 14 generates a magnetic field for magnetically coupling the programming coil 14 with the tag coil 12 of the RFID device 10. When the programming coil 14 and tag coil 12 are magnetically coupled with each other, the unique sequence of a programming signal is sent by the programming coil 14 and received by the tag coil 12. This programming signal is used to program the RFID device 10.

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