公开(公告)号：KR1020120134215A

公开(公告)日：2012-12-12

申请号：KR1020110052992

申请日：2011-06-01

Applicant: 삼성전자주식회사

Inventor： 박상욱 ,  이광용 ,  송호건

IPC: H01L21/60

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03003 ,  H01L2224/03334 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06153 ,  H01L2924/01327 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L21/64 ,  H01L21/67 ,  H01L21/67005 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: A manufacturing method for a semiconductor device is provided to improve performance by minimizing contact resistance between a rewiring layer and a metal pad. CONSTITUTION: A semiconductor substrate, on which a metal pad and a passivation layer(200) are formed, is prepared. The metal pad comprises a circuit part on an upper side thereof and is electrically connected with the circuit part. The passivation layer exposes the metal pad while covering the circuit part. A first rewiring layer(400) is formed with a printing method in order to be extended to the passivation layer on the metal pad. The first rewiring layer is electrically connected with the metal pad. A second rewiring layer is formed on the first rewiring layer with an electroplating method using the first rewiring layer as a seed.

Abstract translation: 目的：提供一种用于半导体器件的制造方法，通过使接线层和金属焊盘之间的接触电阻最小化来提高性能。 构成：制备其上形成金属焊盘和钝化层（200）的半导体衬底。 金属焊盘包括在其上侧的电路部分，并与电路部分电连接。 钝化层在覆盖电路部分的同时暴露金属焊盘。 第一再布线层（400）用印刷方法形成，以便延伸到金属垫上的钝化层。 第一重新布线层与金属垫电连接。 使用第一重新布线层作为种子的电镀方法在第一重新布线层上形成第二重新布线层。

公开(公告)号：KR1020120035719A

公开(公告)日：2012-04-16

申请号：KR1020100097415

申请日：2010-10-06

Applicant: 삼성전자주식회사

Inventor： 이택훈 ,  김원근 ,  장동현 ,  송호건 ,  임성준

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L24/98 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: PURPOSE: A semiconductor package and a manufacturing method thereof are provided to minimize a vulnerable part of a molding layer through a protruded part, thereby reducing damage of the semiconductor package. CONSTITUTION: A first cutoff groove is formed between first semiconductor chips(C1). Second semiconductor chips(C2) are respectively attached to the first semiconductor chips. A molding layer(80) is formed in order to fill the first cutoff groove. A second cutoff groove is formed on the molding layer. The second cutoff groove has a second cutoff width smaller than a first cutoff width.

Abstract translation: 目的：提供一种半导体封装及其制造方法，以通过突出部来最小化成型层的易损部分，从而减少半导体封装的损坏。 构成：在第一半导体芯片（C1）之间形成第一切断槽。 第二半导体芯片（C2）分别安装在第一半导体芯片上。 形成成型层（80）以填充第一切断槽。 在成型层上形成第二切断槽。 第二截止槽具有小于第一截止宽度的第二截止宽度。

公开(公告)号：KR1020110062482A

公开(公告)日：2011-06-10

申请号：KR1020090119223

申请日：2009-12-03

Applicant: 삼성전자주식회사

Inventor： 유황복 ,  정기현 ,  박재용 ,  송호건

IPC: H01L21/60 ,  H01L23/48 ,  H01L23/12

CPC classification number: H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/49 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: PURPOSE: A method for forming a bonding structure is provided to increase contact areas between contact balls and bonding pads by compressing the neck parts of wires to the edge parts of pre-contacting balls in the wires to form contact balls. CONSTITUTION: A bonding structure(122) electrically connects a semiconductor chip(100) and a wiring board(104). A bonding pad(102) electrically connects a memory device and a logic device. The bonding pad is formed at the edge part or the center part of the semiconductor chip. An electrode pad(106) is formed on the wiring board. The bonding structure electrically connects the bonding pad and the electrode pad. The bonding structure includes contact ball(120) and a wire(114).

Abstract translation: 目的：提供一种用于形成接合结构的方法，以通过将电线的颈部部分压缩到电线中预接触球的边缘部分来形成接触球，以增加接触球和接合焊盘之间的接触面积。 结构：接合结构（122）电连接半导体芯片（100）和布线板（104）。 接合焊盘（102）电连接存储器件和逻辑器件。 接合焊盘形成在半导体芯片的边缘部分或中心部分。 电极焊盘（106）形成在布线板上。 接合结构将接合焊盘和电极焊盘电连接。 接合结构包括接触球（120）和线（114）。

公开(公告)号：KR1020080014302A

公开(公告)日：2008-02-14

申请号：KR1020060075808

申请日：2006-08-10

Applicant: 삼성전자주식회사

Inventor： 김학성 ,  송호건 ,  한만희 ,  김희석

IPC: H01L21/58

CPC classification number: H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for attaching a die using fiber reinforced polymer is provided to prevent a die warpage phenomenon in a thin die by attaching the fiber reinforced polymer with a high intensity to a substrate in parallel to a direction of the die warpage. A method for attaching a die using fiber reinforced polymer(20) comprises the steps of: sticking the fiber reinforced polymer on a rear side of a substrate(10) which a plurality of semiconductor chips are formed on; dicing the substrate where the fiber reinforced polymer is stuck to a separated die(12); and attaching the die to a substrate for a package or to a different die using the fiber reinforced polymer on the rear side of the die. The step of attaching the die comprises the steps of: mounting the die on the substrate for the package or on the different die; and hardening the fiber reinforced polymer between the mounted die and the substrate for the package or the different die.

Abstract translation: 提供一种使用纤维增强聚合物附着模具的方法，以通过将平行于模具翘曲的方向将高强度的纤维增强聚合物附着于基底来防止薄模具中的模具翘曲现象。 使用纤维增强聚合物（20）附接模具的方法包括以下步骤：将纤维增强聚合物粘贴在形成多个半导体芯片的基板（10）的后侧; 对纤维增强聚合物粘附到分离的模具（12）上的基底进行切割; 并且使用模具后侧上的纤维增强聚合物将模具附接到用于封装的基板或者使用不同的管芯。 安装模具的步骤包括以下步骤：将管芯安装在用于封装的基板上或在不同的管芯上; 并且在所安装的管芯和用于封装或不同管芯的衬底之间硬化纤维增强聚合物。

公开(公告)号：KR1020070014761A

公开(公告)日：2007-02-01

申请号：KR1020050069662

申请日：2005-07-29

Applicant: 삼성전자주식회사

Inventor： 고준영 ,  송호건 ,  임재윤 ,  천대상

IPC: H01L23/48

CPC classification number: B23K20/007 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/786 ,  H01L2224/85045 ,  H01L2224/851 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85947 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A wire bonding method is provided to reduce a damage to a bonding pad or a collapse of an interlayer dielectric even if a low dielectric material is used as an interlayer dielectric or copper with high hardness is used as a wire, by reducing the force applied to a bonding pad during a bonding process. Bonding balls are formed at the front end of a wire(120) protruding from a capillary(150) wherein spark discharge happens at the front end of the wire by making a torch rod come in contact with the wire while a potential is applied to the wire. The bonding surface of the bonding balls is transformed into a flat disc type. The bonding balls having the bonding surface of the disc type are bonded to the bonding pad.

Abstract translation: 即使使用低电介质材料作为层间电介质，也可以使用引线接合方法来减少接合焊盘的损坏或层间电介质的塌陷，或者通过降低施加到 在接合过程中的接合焊盘。 接合球形成在从毛细管（150）突出的线（120）的前端处，其中通过使焊炬与电线接触而在电线的前端发生火花放电，同时向 线。 接合球的接合面变成平板型。 具有盘型接合面的接合球接合到接合焊盘。

公开(公告)号：KR1020170120257A

公开(公告)日：2017-10-31

申请号：KR1020160048377

申请日：2016-04-20

Applicant: 삼성전자주식회사

Inventor： 이용관 ,  염근대 ,  이종호 ,  송호건

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/16141 ,  H01L2225/06517 ,  H01L2225/06572

Abstract: 패키지모듈기판및 반도체모듈이제공된다. 반도체모듈은제1 영역및 제2 영역을포함하는모듈기판; 상기모듈기판의제1 영역상에실장되는제1 기판; 및상기제1 기판의상면상의제1 탭을포함할수 있다. 상기모듈기판은상기제1 기판을통하여상기제1 탭과전기적으로연결될수 있다.

Abstract translation: 提供封装模块衬底和半导体模块。 一种半导体模块包括：包括第一区域和第二区域的模块基板; 安装在模块衬底的第一区域上的第一衬底; 以及第一基板的上表面上的第一突片。 模块基板可以通过第一基板电连接到第一接头。

公开(公告)号：KR101774234B1

公开(公告)日：2017-09-05

申请号：KR1020110052992

申请日：2011-06-01

Applicant: 삼성전자주식회사

Inventor： 박상욱 ,  이광용 ,  송호건

IPC: H01L21/60

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03003 ,  H01L2224/03334 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06153 ,  H01L2924/01327 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: 재배선층을가지는반도체소자의제조방법을개시한다. 본발명의일 실시예에따른반도체소자의제조방법은상면에회로부가형성되며회로부와전기적으로연결되는금속패드및 회로부를덮으며금속패드를노출시키는보호층(passivation layer)이형성된반도체기판을준비하는단계, 금속패드와전기적으로연결되며, 금속패드상에서보호층상으로연장되도록프린팅방법에의하여제1 재배선층을형성하는단계, 및제1 재배선층을시드로제1 재배선층상에전기도금으로제2 재배선층을형성하는단계를포함한다.

公开(公告)号：KR1020120091694A

公开(公告)日：2012-08-20

申请号：KR1020110011616

申请日：2011-02-09

Applicant: 삼성전자주식회사

Inventor： 박상욱 ,  송호건 ,  이광용

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2225/1011 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012

Abstract: PURPOSE: A semiconductor package is provided to rapidly process data by forming a metal wire on an insulation layer to reduce a signal path. CONSTITUTION: A substrate(100) includes a top surface and a bottom surface. A first semiconductor chip(200) includes an active surface and an inactive surface facing the active surface. An adhesive layer(210) is formed on the inactive surface of the first semiconductor chip. A first via(400) electrically connects a first metal wire(110) to a second metal wire(310). A second via(600) electrically connects the first semiconductor chip to the second metal wire.

Abstract translation: 目的：提供半导体封装以通过在绝缘层上形成金属线来快速处理数据以减少信号路径。 构成：衬底（100）包括顶表面和底表面。 第一半导体芯片（200）包括有源表面和面向有源表面的无效表面。 在第一半导体芯片的非活性表面上形成粘合剂层（210）。 第一通孔（400）将第一金属线（110）电连接到第二金属线（310）。 第二通孔（600）将第一半导体芯片电连接到第二金属线。

公开(公告)号：KR1020120091691A

公开(公告)日：2012-08-20

申请号：KR1020110011613

申请日：2011-02-09

Applicant: 삼성전자주식회사

Inventor： 정세영 ,  송호건 ,  최주일 ,  피재현

IPC: H01L23/10 ,  H01L23/12 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/10135 ,  H01L2224/11015 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13171 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27436 ,  H01L2224/27622 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/81862 ,  H01L2224/81986 ,  H01L2224/83862 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/3511 ,  H01L2924/3651 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: PURPOSE: A semiconductor device with a junction pattern for preventing a warpage and a manufacturing method thereof are provided to form various joints of semiconductor devices by electroless plating with a strip unit of a printed circuit board. CONSTITUTION: A first semiconductor device(100) includes an I/O terminal(20) which extends a function of a circuit pattern(13) of a semiconductor device. A top I/O pad(40) is formed on the upper side(11) of the first semiconductor device. A bottom I/O pad(60) is formed on the lower side(12) of the first semiconductor substrate. A second semiconductor device(200) is bonded to the first semiconductor device. A junction pattern(70A) for preventing the warpage is arranged in a space between the first semiconductor device and the second semiconductor device.

Abstract translation: 目的：提供具有用于防止翘曲的接合图案的半导体器件及其制造方法，以通过利用印刷电路板的带状单元的无电镀来形成半导体器件的各种接合。 构成：第一半导体器件（100）包括延伸半导体器件的电路图案（13）的功能的I / O端子（20）。 顶部I / O焊盘（40）形成在第一半导体器件的上侧（11）上。 底部I / O焊盘（60）形成在第一半导体衬底的下侧（12）上。 第二半导体器件（200）被接合到第一半导体器件。 用于防止翘曲的接合图案（70A）布置在第一半导体器件和第二半导体器件之间的空间中。

公开(公告)号：KR1020120058114A

公开(公告)日：2012-06-07

申请号：KR1020100119757

申请日：2010-11-29

Applicant: 삼성전자주식회사

Inventor： 이호진 ,  조태제 ,  장동현 ,  송호건 ,  정세영 ,  강운병 ,  윤민승

IPC: H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: PURPOSE: A semiconductor device, a manufacturing method thereof, and a semiconductor package including the same are provided to prevent a semiconductor substrate and a penetrating electrode to be shorted by preventing the damage of a via hole insulating layer when eliminating a first insulating layer of penetrating via. CONSTITUTION: A semiconductor substrate(10) comprises a first side(11) and a second side(12) opposed to the first side. An integrated circuit(13) is formed on the first side of the semiconductor substrate. A via hole(16) is separated from the integrated circuit and is provided within the semiconductor substrate. A penetrating electrode(20) comprises a conductive connection unit(26) and a barrier layer(24). The barrier layer is formed at the inner wall of the via hole. A trench(103) is formed at the second side of the semiconductor substrate. A re-wire(45) is electrically connected with the penetrating electrode.

Abstract translation: 目的：提供一种半导体器件及其制造方法以及包含该半导体器件的半导体封装，以防止半导体衬底和穿透电极在消除穿透绝缘层的第一绝缘层时通过防止通孔绝缘层的损坏来短路 通过。 构成：半导体衬底（10）包括与第一侧相对的第一侧（11）和第二侧（12）。 在半导体衬底的第一侧上形成集成电路（13）。 通孔（16）与集成电路分离并设置在半导体衬底内。 穿透电极（20）包括导电连接单元（26）和阻挡层（24）。 阻挡层形成在通孔的内壁。 沟槽（103）形成在半导体衬底的第二侧。 再线（45）与穿透电极电连接。