公开(公告)号：KR1020100075209A

公开(公告)日：2010-07-02

申请号：KR1020080133843

申请日：2008-12-24

Applicant: 삼성전자주식회사

Inventor： 이명재 ,  안승언 ,  이창범

IPC: H01L27/10

Abstract: PURPOSE: A memory device is provided to implement high integration and a performance memory device by interposing a sub substrate with a peripheral circuit between memory arrays which are formed on a main substrate with a low temperature process. CONSTITUTION: A plurality of memory arrays(M1-M12) is laminated on a main substrate(SUB1). One or more peripheral circuit units are interposed between memory arrays. The peripheral circuit unit comprises a single crystal substrate and a peripheral circuit formed on the sub substrate. A first peripheral circuit is formed on the lower side of a first sub substrate. The peripheral circuit unit includes a second sub substrate and a second peripheral circuit. The second sub substrate is formed on the upper side of the first sub substrate. The second peripheral circuit is formed on the upper side of the second sub substrate.

Abstract translation: 目的：提供存储器件以实现高集成度和性能存储器件，其通过在低温处理的主衬底上形成的存储器阵列之间插入具有外围电路的子衬底。 构成：在主基板（SUB1）上层叠多个存储器阵列（M1-M12）。 一个或多个外围电路单元插入在存储器阵列之间。 外围电路单元包括形成在副基板上的单晶基板和外围电路。 第一外围电路形成在第一子基板的下侧。 外围电路单元包括第二子基板和第二外围电路。 第二子基板形成在第一子基板的上侧。 第二外围电路形成在第二副基板的上侧。

公开(公告)号：KR1020090080751A

公开(公告)日：2009-07-27

申请号：KR1020080006702

申请日：2008-01-22

Applicant: 삼성전자주식회사

Inventor： 김기환 ,  박영수 ,  이명재 ,  선우문욱 ,  안승언 ,  이창범

IPC: H01L27/115

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675 ,  G11C13/0004

Abstract: A resistive memory device is provided to prevent thermal degradation of a diode and a resistance change layer by including a protecting layer. A resistive memory device includes a storage node, a switching device, and a protecting layer(140). The storage node includes a resistance change layer(110). The switching device is connected to the storage node. The protecting layer covers a part exposed of the resistance change layer, is made of material which does not a silicide reaction with the resistance change layer, is a material layer which prevents hydrogen permeation, and includes at least one among aluminum oxide and titanium oxide. The resistance change layer is a metal oxide layer.

Abstract translation: 提供电阻式存储器件以通过包括保护层来防止二极管和电阻变化层的热劣化。 电阻式存储器件包括存储节点，开关器件和保护层（140）。 存储节点包括电阻变化层（110）。 交换设备连接到存储节点。 保护层覆盖暴露于电阻变化层的部分，由与电阻变化层不发生硅化物反应的材料制成，是防止氢渗透的材料层，并且包括氧化铝和氧化钛中的至少一种。 电阻变化层是金属氧化物层。

公开(公告)号：KR1020090027561A

公开(公告)日：2009-03-17

申请号：KR1020080047092

申请日：2008-05-21

Applicant: 삼성전자주식회사 ,  성균관대학교산학협력단

Inventor： 박재철 ,  권기원 ,  박영수 ,  이승훈 ,  안승언

IPC: G11C17/00 ,  H01L21/8239 ,  H01L23/12

CPC classification number: G11C5/02 ,  G11C5/063 ,  G11C8/10 ,  G11C8/14

Abstract: A multi-layered memory apparatus is provided to improve a data storage density by forming one or more memory layer by a plurality of sub arrays. A multi-layered memory apparatus includes two or more memory parts(12) and an active circuit part(11). The active circuit part includes a decoder, and is formed between the memory parts. The memory part includes one or more memory layer. The memory layer is a memory array of a cross point type, and has a plurality of sub arrays. The active circuit part is formed on a non-silicone substrate. The non-silicone substrate is made of plastic, glass, ceramic, oxide material, or nitride material.

Abstract translation: 提供一种多层存储装置，通过由多个子阵列形成一个或多个存储层来提高数据存储密度。 多层存储装置包括两个或多个存储器部件（12）和有源电路部件（11）。 有源电路部分包括解码器，并且形成在存储器部分之间。 存储器部分包括一个或多个存储器层。 存储层是交叉点类型的存储器阵列，并且具有多个子阵列。 有源电路部分形成在非硅衬底上。 非硅树脂基材由塑料，玻璃，陶瓷，氧化物材料或氮化物材料制成。

公开(公告)号：KR1020070090328A

公开(公告)日：2007-09-06

申请号：KR1020060019915

申请日：2006-03-02

Applicant: 삼성전자주식회사

Inventor： 이명재 ,  유인경 ,  이은홍 ,  김종완 ,  김동철 ,  안승언

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/1021 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/73

Abstract: An NVM(non-volatile memory) device is provided to simplify the structure of a cell by eliminating the necessity for a separate switching device such as a transistor or a diode in a unit cell structure. A first-type semiconductor oxide layer(22) is formed on a lower electrode. A second-type semiconductor oxide layer(23) is formed on the first-type semiconductor oxide layer. An upper electrode is formed on the second-type semiconductor oxide layer. The first-type or second-type semiconductor oxide layer can be made of a p-type or n-type semiconductor. The first-type or second-type semiconductor oxide layer can be made of a transition metal oxide.

Abstract translation: 提供了一种NVM（非易失性存储器）器件，以通过消除单元电路结构中的诸如晶体管或二极管之类的单独开关器件的必要性来简化单元的结构。 第一型半导体氧化物层（22）形成在下电极上。 在第一型半导体氧化物层上形成第二类型的半导体氧化物层（23）。 上电极形成在第二类半导体氧化物层上。 第一类型或第二类型半导体氧化物层可以由p型或n型半导体制成。 第一类型或第二类型半导体氧化物层可以由过渡金属氧化物制成。

公开(公告)号：KR100682908B1

公开(公告)日：2007-02-15

申请号：KR1020040109268

申请日：2004-12-21

Applicant: 삼성전자주식회사

Inventor： 정용수 ,  박윤동 ,  유인경 ,  이명재 ,  서순애 ,  김혜영 ,  안승언 ,  서형석

IPC: H01L27/115 ,  H01L27/10

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/76 ,  G11C2213/77 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile memory device having two or more resistors and methods of forming and using the same. A nonvolatile memory device having two resistance layers, and more particularly, to a nonvolatile memory device formed and operated using a resistance layer having memory switching characteristics and a resistance layer having threshold switching characteristics. The nonvolatile semiconductor memory device may include a lower electrode; a first resistance layer having at least two resistance characteristics formed on the lower electrode, a second resistance layer having threshold switching characteristics formed on the first resistance layer, and an upper electrode formed on the second resistance layer.

公开(公告)号：KR1020060091650A

公开(公告)日：2006-08-21

申请号：KR1020050012915

申请日：2005-02-16

Applicant: 삼성전자주식회사

Inventor： 강윤호 ,  이은혜 ,  이명재 ,  서순애 ,  안승언

IPC: H01L27/115

CPC classification number: H01L21/28282 ,  B82Y10/00 ,  G11C16/0416 ,  H01L29/51 ,  H01L29/513 ,  H01L29/792 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825

Abstract: 비휘발성 메모리 소자 및 그 제조방법이 개시된다. 본 발명에 따르면, 소오스 및 드레인 영역과 채널영역이 마련된 반도체 기판, 상기 채널영역 위에 형성된 터널링 산화막, 상기 터널링 산화막 위에 전이금속 산화물로 형성된 플로우팅 게이트, 상기 플로우팅 게이트 위에 형성된 블로킹 산화막 및 상기 블로킹 산화막 위에 형성된 게이트전극을 포함하는 비휘발성 메모리 소자 및 그 제조방법이 제공된다.

公开(公告)号：KR102237820B1

公开(公告)日：2021-04-08

申请号：KR1020140057952

申请日：2014-05-14

Applicant: 삼성전자주식회사

Inventor： 안지훈 ,  전용우 ,  김정우 ,  박해석 ,  안승언 ,  이승협 ,  정명훈 ,  최혁순

IPC: H01L27/146

Abstract: 개시된수평형포토다이오드는기판; 상기기판상에형성된절연마스크층; 상기절연마스크층의일면에접촉하며, 상기일면과나란한방향을따라순차배치된제1형반도체층, 활성층, 제2형반도체층;을포함한다. 상기절연마스크층은관통홀이구비되어, 상기제1형반도체층, 활성층, 제2형반도체층이상기관통홀로부터측면과성장법에의해형성된다.

公开(公告)号：KR101951322B1

公开(公告)日：2019-02-22

申请号：KR1020170172314

申请日：2017-12-14

Applicant: 삼성전자주식회사

Inventor： 김영 ,  송이헌 ,  안승언 ,  전상훈

IPC: G06F3/042 ,  H01L27/146 ,  H01L31/113 ,  G06F3/041 ,  H01L29/786

公开(公告)号：KR101902929B1

公开(公告)日：2018-10-01

申请号：KR1020120081438

申请日：2012-07-25

Applicant: 삼성전자주식회사

Inventor： 안승언 ,  송이헌

IPC: G06F3/044 ,  G09G3/36

CPC classification number: G06F3/044 ,  G06F3/0412 ,  G06F3/0416

Abstract: 본발명의실시예에따른터치패널은, 제1 전극및 제2 전극의전압차이로액정을구동하고, 디스플레이게이트라인의활성화에응답하여, 디스플레이하고자하는이미지전압을생성하여상기제1 전극에인가하는디스플레이부; 및센서게이트라인의활성화에응답하여, 상기터치패널에대한물리적터치에따른핑거커패시턴스의발생여부를상기제2 전극의전압변화를통해센싱하는센싱부를포함한다.

公开(公告)号：KR101786567B1

公开(公告)日：2017-10-19

申请号：KR1020110023432

申请日：2011-03-16

Applicant: 삼성전자주식회사

Inventor： 안승언 ,  송이헌 ,  김창정 ,  전상훈

IPC: H04Q9/00 ,  G06F3/041

Abstract: 광터치스크린용리모트컨트롤러및 그동작방법이개시된다. 개시된광 터치스크린용리모트컨트롤러는레이저광원부, 레이저광의진행경로에있는인체를감지하기위한인체감지센서, 및인체감지센서의출력에따라레이저광원부의동작을제어하는제어모듈을포함한다. 개시된광 터치스크린용리모트컨트롤러는인체감지센서를통해일정각도범위내에서인체를감지하면, 제어모듈이레이저광원부의동작을제한함으로써레이저광이인체를향해방출되지않도록할 수있다. 따라서, 레이저광에의한사용자의시력저하나훼손을방지할수 있다.