公开(公告)号：KR1020150057226A

公开(公告)日：2015-05-28

申请号：KR1020130140281

申请日：2013-11-19

Applicant: 삼성전자주식회사

Inventor： 남필욱 ,  양준규 ,  김진균 ,  안재영 ,  임헌형 ,  황기현

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L29/66833 ,  H01L29/7926 ,  H01L27/11553

Abstract: 수직형메모리장치의제조방법에있어서, 기판상에층간절연막및 폴리실리콘또는비정질실리콘을포함하는희생막을교대로반복적으로적층한다. 층간절연막들및 희생막들을관통하여기판상면을노출시키는채널홀들을형성한다. 채널홀 내부에채널을형성한다. 채널과인접한층간절연막들및 희생막들부분을식각하여기판상면을노출시키는개구부들을형성한다. 희생막들을제거하여층간절연막들사이에갭을형성한다. 갭을채우는게이트라인들을형성한다. 층간절연막에비해식각선택비가높은물질을사용하여희생막을형성함으로써희생막을선택적으로제거할수 있다.

Abstract translation: 垂直存储器件的制造方法重复地和交替地在衬底上堆叠层绝缘膜和包括多晶硅或非晶硅的牺牲膜。 形成通过穿过层绝缘膜和牺牲膜而暴露衬底的上侧的通道孔。 在通道孔内形成通道。 形成通过蚀刻层间绝缘膜和邻近通道的牺牲膜露出衬底的上侧的开口。 通过去除牺牲膜在层间绝缘膜上形成间隙。 形成填充有间隙的栅极线。 通过使用具有比层间绝缘膜高的蚀刻选择比的材料，通过形成牺牲膜来选择性地除去牺牲膜。

公开(公告)号：KR1020140105954A

公开(公告)日：2014-09-03

申请号：KR1020130019786

申请日：2013-02-25

Applicant: 삼성전자주식회사

Inventor： 김진균 ,  안재영 ,  황기현

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/7926 ,  H01L27/11582 ,  H01L29/66833 ,  H01L21/823487 ,  H01L27/11578

Abstract: A vertical memory device comprises a channel array, a charge storage film structure, a plurality of gate electrodes, and a dummy pattern array. The channel array is formed on a first area of a substrate and includes a plurality of channels individually extended in a first direction perpendicular to the upper surface of the substrate. The charge storage film structure includes a tunnel insulation film pattern, the charge storage film structure, and a blocking film pattern sequentially stacked on sidewalls of respective channels in a second direction parallel with the upper surface of the substrate. The gate electrodes are arranged to be apart from each other in the first direction on the sidewall of the respective charge storage film structure. The dummy pattern array is formed on a second area of the substrate adjacent to the first area and includes a plurality of dummy patterns individually extended in the first direction.

Abstract translation: 垂直存储器件包括沟道阵列，电荷存储膜结构，多个栅电极和虚拟图案阵列。 沟道阵列形成在衬底的第一区域上，并且包括沿垂直于衬底的上表面的第一方向单独延伸的多个通道。 电荷存储膜结构包括隧道绝缘膜图案，电荷存储膜结构和依次层叠在各个沟道的侧壁上的阻挡膜图案，该第二方向与基板的上表面平行。 栅电极被布置为在相应的电荷存储膜结构的侧壁上沿第一方向彼此分开。 伪图案阵列形成在与第一区域相邻的基板的第二区域上，并且包括在第一方向上分别延伸的多个虚设图案。

公开(公告)号：KR1020140027862A

公开(公告)日：2014-03-07

申请号：KR1020130004203

申请日：2013-01-15

Applicant: 삼성전자주식회사

Inventor： 남필욱 ,  양준규 ,  안재영 ,  장병현 ,  황기현

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11582 ,  H01L21/02252 ,  H01L21/76877 ,  H01L21/823487 ,  H01L27/11578 ,  H01L29/7926

Abstract: A vertical type semiconductor device is protruding from the top surface of a substrate in a vertical direction and includes a pillar structure having a semiconductor pattern and a channel pattern. A first word line structure horizontally extends while surrounding the pillar structure on the part facing the channel pattern, in which includes a blocking dielectric layer and a metal pattern, and having a shape in which a height is extended on the part touching the pillar structure is provided. Furthermore, a first insulation film structure interposed between the first word line structures in a first direction while surrounding the pillar structure and having a first part touching the pillar structure while having a relatively low height and a second part horizontally extended in a lateral direction of the first part is provided. The vertical type semiconductor device is capable of increasing the laminated stage number of cells as the height of each cell is reduced. [Reference numerals] (AA) First direction; (BB) Second direction; (CC) Third direction

Abstract translation: 垂直型半导体器件在垂直方向上从衬底的顶表面突出并且包括具有半导体图案和沟道图案的柱结构。 第一字线结构在包围阻挡电介质层和金属图案的部分面向沟道图案的部分处水平延伸，并且在接触柱结构的部分上具有高度延伸的形状 提供。 此外，第一绝缘膜结构在第一方向上插入在第一字线结构之间，同时围绕柱结构，并且具有接触柱结构的第一部分，同时具有相对较低的高度;以及第二部分沿第二方向在水平方向延伸 提供第一部分。 随着每个单元的高度减小，垂直型半导体器件能够增加单元的层叠台数。 （附图标记）（AA）第一方向; （BB）第二方向; （CC）第三方向

公开(公告)号：KR1020130116604A

公开(公告)日：2013-10-24

申请号：KR1020120039151

申请日：2012-04-16

Applicant: 삼성전자주식회사

Inventor： 이주열 ,  김범수 ,  박광민 ,  박현 ,  안재영 ,  유동철 ,  전종식 ,  황기현

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L29/7926 ,  H01L21/823487 ,  H01L27/0688

Abstract: PURPOSE: A three dimensional semiconductor memory device and a method for fabricating the same are provided to improve a charge retention property by reducing the loss of charges stored in a charge storage layer. CONSTITUTION: A laminate structure (200) includes gate patterns (160) and insulating patterns (112). The laminate structure has a sidewall. A channel structure (210) passes through the sidewall of the laminate structure and connected to a substrate. A data storage layer is formed between the laminate structure and the channel structure. The data storage layer conformally covers the side wall of the laminate structure.

Abstract translation: 目的：提供三维半导体存储器件及其制造方法，以通过减少存储在电荷存储层中的电荷损失来提高电荷保留性能。 构成：层压结构（200）包括栅极图案（160）和绝缘图案（112）。 层压结构具有侧壁。 通道结构（210）穿过层叠结构的侧壁并连接到基底。 在层叠结构和通道结构之间形成数据存储层。 数据存储层保形地覆盖层压结构的侧壁。

公开(公告)号：KR1020130057670A

公开(公告)日：2013-06-03

申请号：KR1020110123530

申请日：2011-11-24

Applicant: 삼성전자주식회사

Inventor： 양준규 ,  남필욱 ,  황기현 ,  안재영 ,  김진균 ,  임승현

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/1157 ,  H01L27/11582 ,  H01L21/76205 ,  H01L21/823487 ,  H01L27/0688

Abstract: PURPOSE: A semiconductor memory device and a method for fabricating the same are provided to secure stable current paths by stably connecting a lower channel to an upper channel. CONSTITUTION: A gate is laminated on a substrate. A vertical channel includes an upper channel(142) and a lower channel(141). The upper channel and the lower channel are electrically connected to the substrate. An information storage layer(151,152) is arranged between the vertical channel and the gate. The upper channel includes a vertical pattern and a horizontal pattern.

Abstract translation: 目的：提供半导体存储器件及其制造方法，以通过将下通道稳定地连接到上通道来确保稳定的电流路径。 构成：将栅极层压在基板上。 垂直通道包括上通道（142）和下通道（141）。 上通道和下通道电连接到基板。 信息存储层（151,152）布置在垂直通道和门之间。 上部通道包括垂直图案和水平图案。

公开(公告)号：KR1020110021238A

公开(公告)日：2011-03-04

申请号：KR1020090078906

申请日：2009-08-25

Applicant: 삼성전자주식회사

Inventor： 양준규 ,  안재영 ,  박영근 ,  황기현 ,  신동운 ,  이주열

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/513 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L21/02362

Abstract: PURPOSE: A non-volatile memory and a forming method thereof are provided to improve the retention property of a device by alleviating the electrical field applied to the edge of the active area by comprising a barrier capping layer. CONSTITUTION: A semiconductor substrate(100) including an element separation layer(105) is prepared for defining the active area. A tunnel insulating layer(110) is formed on the semiconductor substrate of the active area. A charge trapping layer(120) is formed on the tunnel insulating layer. A blocking insulation film(140) is formed on the charge trapping layer and the element isolation film.

Abstract translation: 目的：提供一种非易失性存储器及其形成方法，以通过包括阻挡覆盖层减轻施加到有源区域的边缘的电场来改善器件的保持性。 构成：准备包括元件分离层（105）的半导体衬底（100）以限定有效面积。 隧道绝缘层（110）形成在有源区的半导体衬底上。 电荷俘获层（120）形成在隧道绝缘层上。 在电荷捕获层和元件隔离膜上形成阻挡绝缘膜（140）。

公开(公告)号：KR100706790B1

公开(公告)日：2007-04-12

申请号：KR1020050116482

申请日：2005-12-01

Applicant: 삼성전자주식회사

Inventor： 황기현 ,  정우인 ,  신유균 ,  안재영 ,  김진균

IPC: H01L21/316

Abstract: 본 발명은 산화 처리를 수행하는 장치를 제공한다. 장치는 처리실과 로드록 챔버를 가진다. 처리실에는 그 내부로 오존을 공급하는 오존 공급 유닛이 설치된다. 오존 공급 유닛은 처리실 외부에 배치되며 오존을 발생하는 오존 발생기와 처리실 내부에 배치되며 오존을 처리실 내부로 분사하는 오존 분사 노즐을 가진다. 오존 분사 노즐의 둘레에는 오존 분사 노즐 내 오존을 냉각하는 냉각 유체가 흐르는 냉각관이 설치된다. 상술한 구조로 인해 오존은 오존 분사 노즐 내에서 수명이 연장되어 웨이퍼들 전체로 대체로 균일하게 공급될 수 있다. 또한, 처리실 내로 산소와 수소를 공급하지 않고 처리실 외부에서 오존을 발생하여 처리실 내로 공급하므로 수소가 없는 분위기에서 산화 공정 수행이 가능하며, 이로 인해 산화 공정에 의해 웨이퍼 상에 형성된 산화막의 신뢰도가 매우 높다.
산화 처리, 산화막, 오존, 수소

Abstract translation: 本发明提供了一种用于进行氧化处理的装置。 该装置有一个处理室和一个负载锁定室。 处理室设有用于向其内部供应臭氧的臭氧供应单元。 臭氧供应单元设置在处理室外部，并具有用于产生臭氧的臭氧发生器和设置在处理室内用于将臭氧喷射到处理室内的臭氧喷雾喷嘴。 在臭氧喷射喷嘴的周围设置有用于冷却臭氧喷射喷嘴内的臭氧的冷却流体的冷却管。 由于上述结构，通过延长臭氧喷雾喷嘴的寿命，臭氧可以基本上均匀地供应到整个晶片。 另外，由于在处理室臭氧的产生以外不供给氧气和氢气进入供给到能够在没有氢的气氛中，这会导致形成在晶片上的氧化膜具有非常高的可靠性，通过氧化工艺进行氧化处理的处理腔室中的处理室 。

公开(公告)号：KR1020070032833A

公开(公告)日：2007-03-23

申请号：KR1020050087173

申请日：2005-09-20

Applicant: 삼성전자주식회사

Inventor： 김홍석 ,  양상렬 ,  황기현 ,  노진태 ,  안재영 ,  김진균 ,  이성해 ,  이은호

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/67069 ,  H01L21/76224

Abstract: A method for manufacturing a nonvolatile memory apparatus is provided to facilitate deposition of a dielectric and a control gate electrode layer by expanding an interval between floating gate electrodes, and an inner width thereof. An isolation layer(108) is formed on a substrate(100) to define an active region(104) and a field region on the substrate. A tunnel oxide layer(112) is formed on a surface of the substrate of the active region. A sacrificial layer pattern(120) having an opening unit is formed. The opening unit exposes the tunnel oxide layer and the substrate of the field region. A conductive layer(124) is successively formed on a surface of the tunnel oxide layer, a sidewall of the opening unit, and a surface of the sacrificial layer pattern. The opening unit where the conductive layer is formed is fully gap-filled to form a gap-fill layer(128) consisting of an HDP-CVD oxide layer, USG, BPSG, or SOG. The conductive layer and the gap-fill layer are planarized when the surface of the sacrificial layer pattern is exposed to form a preliminary conductive layer pattern. The preliminary conductive layer pattern is connected to both edges of the first conductive layer pattern in a body and has a second conductive layer pattern extended to a vertical direction. The sacrificial layer pattern and the part of the planarized gap-fill layer are firstly etched to expose the second conductive layer pattern of the preliminary conductive layer pattern. The part of the second conductive layer pattern of the exposed preliminary conductive layer pattern is secondly etched by using the first etched sacrificial layer pattern and the gap-fill layer as etching masks. The first etched gap-fill layer is removed and a part of the first etched sacrificial layer pattern is thirdly etched. The third etched sacrificial layer pattern is removed at the same time the part of the first conductive pattern of the second etched preliminary conductive layer pattern is fourthly etched to form a completed conductive pattern.

Abstract translation: 提供一种用于制造非易失性存储装置的方法，以便通过扩大浮置栅电极之间的间隔及其内部宽度来促进电介质和控制栅电极层的沉积。 隔离层（108）形成在衬底（100）上以在衬底上限定有源区（104）和场区。 隧道氧化物层（112）形成在有源区的衬底的表面上。 形成具有开口单元的牺牲层图案（120）。 开口单元暴露隧道氧化物层和场区域的衬底。 导电层（124）依次形成在隧道氧化物层的表面，开口单元的侧壁和牺牲层图案的表面上。 形成导电层的开口单元被完全间隙填充以形成由HDP-CVD氧化物层，USG，BPSG或SOG组成的间隙填充层（128）。 当牺牲层图案的表面暴露以形成初步导电层图案时，导电层和间隙填充层被平坦化。 初级导电层图案被连接到主体中的第一导电层图案的两个边缘，并且具有向垂直方向延伸的第二导电层图案。 首先蚀刻牺牲层图案和平坦化间隙填充层的一部分以暴露初步导电层图案的第二导电层图案。 通过使用第一蚀刻牺牲层图案和间隙填充层作为蚀刻掩模，第二蚀刻暴露的初级导电层图案的第二导电层图案的部分。 去除第一蚀刻间隙填充层，并且第一蚀刻牺牲层图案的一部分被第三蚀刻。 同时去除第三蚀刻牺牲层图案，同时第二蚀刻初步导电层图案的第一导电图案的部分被第四次蚀刻以形成完整的导电图案。

公开(公告)号：KR1020070014410A

公开(公告)日：2007-02-01

申请号：KR1020050069027

申请日：2005-07-28

Applicant: 삼성전자주식회사

Inventor： 김홍석 ,  황기현 ,  노진태 ,  안재영 ,  김진균 ,  이은호 ,  양상렬

IPC: H01L27/115

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L21/823468 ,  H01L29/42324

Abstract: A method for fabricating an NVM(non-volatile memory) device is provided to prevent a tunnel oxide layer from being deteriorated by depositing a silicon oxide layer on a gate spacer while the silicon oxide layer is not exposed to hydrogen atmosphere. A cell gate(110) in which a tunnel oxide layer(102), a floating gate(104), an interlayer dielectric(106) and a control gate(108) are sequentially stacked is formed on a semiconductor substrate(100). A stack process using SiCl4 gas and N2O gas is performed to continuously form a silicon oxide layer(114) on the sidewall and the upper surface of the cell gate and the upper surface of the semiconductor substrate. A heat treatment is performed in an atmosphere of D2. The silicon oxide layer is anisotropically etched to form a gate spacer made of a silicon oxide layer on the sidewall of the cell gate.

Abstract translation: 提供了一种用于制造NVM（非易失性存储器）器件的方法，以防止在氧化硅层不暴露于氢气氛的同时，在栅极间隔物上沉积氧化硅层，从而恶化隧道氧化物层。 其中隧道氧化物层（102），浮动栅极（104），层间电介质（106）和控制栅极（108）依次层叠的单元栅极（110）形成在半导体衬底（100）上。 执行使用SiCl 4气体和N 2 O气体的堆叠工艺，以在电池栅极的侧壁和上表面以及半导体衬底的上表面上连续形成氧化硅层（114）。 在D2的气氛中进行热处理。 氧化硅层被各向异性地蚀刻以在电池栅极的侧壁上形成由氧化硅层制成的栅极间隔物。

公开(公告)号：KR1020070002235A

公开(公告)日：2007-01-05

申请号：KR1020050057652

申请日：2005-06-30

Applicant: 삼성전자주식회사

Inventor： 김진균 ,  황기현 ,  노진태 ,  안재영 ,  김홍석

IPC: H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/31111 ,  H01L21/823468

Abstract: A method for forming a contact hole of a semiconductor device is provided to reduce contact resistance by increasing a contact area between a conductive material and a semiconductor substrate using an enlarged lower portion of the contact hole. Conductive patterns are formed on a substrate(100). A first thin film made of a first material and a second thin film made of a second material are sequentially deposited on the resultant structure. A spacer structure composed of first and second spacers(116a,118a) is formed at both sidewalls of each conductive pattern by performing an anisotropic etching process on the first and second thin film. An interlayer dielectric is formed thereon. A pre-contact hole for exposing the spacer structure to the outside is formed on the resultant structure by etching selectively the interlayer dielectric. An enlarged contact hole(128) is completed by etching partially the exposed portion of the spacer structure.

Abstract translation: 提供一种用于形成半导体器件的接触孔的方法，通过使用接触孔的较大下部增加导电材料和半导体衬底之间的接触面积来降低接触电阻。 导电图案形成在基板（100）上。 由第一材料制成的第一薄膜和由第二材料制成的第二薄膜依次沉积在所得结构上。 通过对第一和第二薄膜进行各向异性蚀刻处理，在每个导电图案的两个侧壁处形成由第一和第二间隔物（116a，118a）构成的间隔结构。 在其上形成层间电介质。 通过选择性地蚀刻层间电介质，在所得结构上形成用于将间隔结构暴露于外部的预接触孔。 扩大的接触孔（128）通过部分蚀刻间隔结构的暴露部分来完成。