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公开(公告)号：KR1020130049539A
公开(公告)日：2013-05-14
申请号：KR1020110114630
申请日：2011-11-04
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/66636 , H01L21/76224 , H01L29/0657 , H01L29/78 , H01L29/7848 , H01L29/66712
Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to form a space for forming a semiconductor pattern at both sidewalls of an element isolation region. CONSTITUTION: A substrate(100) including a first area and a second area is provided. The first area includes a gate pattern(120). The second area includes a first trench and an insulating layer(110) for filling the first trench(110T). A part of the insulating layer is etched to expose a part of the sidewall of the first trench. A first spacer(130B) is formed in the sidewall of the gate pattern. A second spacer(130A) is formed in the exposed sidewall of the first trench. The first spacer and the second spacer are formed at the same time.
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以在元件隔离区的两个侧壁处形成用于形成半导体图案的空间。 构成：提供包括第一区域和第二区域的基板（100）。 第一区域包括栅极图案（120）。 第二区域包括用于填充第一沟槽（110T）的第一沟槽和绝缘层（110）。 蚀刻绝缘层的一部分以暴露第一沟槽的侧壁的一部分。 第一间隔物（130B）形成在栅极图案的侧壁中。 在第一沟槽的暴露的侧壁中形成第二间隔物（130A）。 第一间隔物和第二间隔物同时形成。
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公开(公告)号：KR1020130010360A
公开(公告)日：2013-01-28
申请号：KR1020110071115
申请日：2011-07-18
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/28
CPC classification number: H01L21/76808 , H01L21/31144 , H01L21/76811 , H01L21/76816
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to stably fill a trench and a via hole with conductive materials by removing a second hard mask pattern after the trench and the via hole are formed. CONSTITUTION: A substrate including a first trench, a first hard mask pattern, and a second hard mask pattern is provided(S110). The first trench is filled by forming filling materials on the interlayer dielectric layer and the second hard mask pattern(S120). The second hard mask pattern is exposed by removing a part of the filling materials(S130). The second hard mask pattern is removed(S140). The remaining filling materials are removed(S150). A wire is formed by filing the first trench with conductive materials(S160). [Reference numerals] (AA) Start; (BB) End; (S100) Providing a substrate including a first trench and first and second hard mask patterns; (S120) Filling the first trench with filling materials; (S130) Exposing the second hard mask pattern by removing a part of the filling materials; (S140) Removing the second hard mask pattern; (S150) Removing the remaining filling materials; (S160) Forming a wire
Abstract translation: 目的：提供一种制造半导体器件的方法，通过在形成沟槽和通孔之后去除第二硬掩模图案来稳定地填充导电材料的沟槽和通孔。 构成：提供包括第一沟槽，第一硬掩模图案和第二硬掩模图案的衬底（S110）。 通过在层间介质层和第二硬掩模图案上形成填充材料填充第一沟槽（S120）。 通过去除一部分填充材料来暴露第二硬掩模图案（S130）。 去除第二硬掩模图案（S140）。 除去剩余的填充材料（S150）。 通过用导电材料填充第一沟槽形成导线（S160）。 （附图标记）（AA）开始; （BB）结束; （S100）提供包括第一沟槽和第一和第二硬掩模图案的衬底; （S120）用填充材料填充第一沟; （S130）通过去除一部分填充材料来暴露第二硬掩模图案; （S140）去除第二硬掩模图案; （S150）取出剩余的填充材料; （S160）形成电线
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公开(公告)号：KR1020120133012A
公开(公告)日：2012-12-10
申请号：KR1020110051465
申请日：2011-05-30
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/28
CPC classification number: H01L21/31144 , H01L21/76804 , H01L21/76808 , H01L21/76811 , H01L21/76877
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to improve reliability of a damascene wire by preventing void to be generated when a conducting material is formed on a barrier layer. CONSTITUTION: A first semiconductor device which includes a first trench, a first mask pattern, and a second hard mask pattern are provided(S100). A filler material is formed in order to fill up the first trench(S110). A first hard mask trimming pattern and a second hard mask trimming pattern are formed by trimming a sidewall of the first hard mask pattern and the second hard mask pattern(S120). A barrier layer is formed on the first hard mask trimming pattern and the second hard mask trimming pattern(S130). A damascene wire is formed by filling the first trench with a conducting material(S140). [Reference numerals] (AA) Start; (BB) End; (S100) Providing a semiconductor device including a first trench, a first hard mask pattern, and a second hard mask pattern; (S110) Forming filling materials to fill a first trench; (S120) Forming a first hard mask trimming pattern and a second hard mask trimming pattern by removing filling materials and trimming the sidewall of the first and second hard mask patterns; (S130) Forming a barrier layer; (S140) Forming a damascene wire
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过在阻挡层上形成导电材料时防止产生空隙来提高镶嵌线的可靠性。 提供了包括第一沟槽，第一掩模图案和第二硬掩模图案的第一半导体器件（S100）。 形成填充材料以填充第一沟槽（S110）。 通过修剪第一硬掩模图案和第二硬掩模图案的侧壁来形成第一硬掩模修剪图案和第二硬掩模修剪图案（S120）。 在第一硬掩模修剪图案和第二硬掩模修剪图案上形成阻挡层（S130）。 通过用导电材料填充第一沟槽形成镶嵌线（S140）。 （附图标记）（AA）开始; （BB）结束; （S100）提供包括第一沟槽，第一硬掩模图案和第二硬掩模图案的半导体器件; （S110）形成填充材料以填充第一沟槽; （S120）通过去除填充材料并修整第一和第二硬掩模图案的侧壁来形成第一硬掩模修剪图案和第二硬掩模修剪图案; （S130）形成阻挡层; （S140）形成镶嵌线
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公开(公告)号：KR1020100092240A
公开(公告)日：2010-08-20
申请号：KR1020090011526
申请日：2009-02-12
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: H01L22/14
Abstract: PURPOSE: The wafer testing method and wafer inspection system measure the electric resistance of the second between electrode which is close with the electrolyte and the first electrode which is electrically close with the containing film pattern. The corrosion index is grasped. CONSTITUTION: The wafer(W) including the chip area in which the metal film pattern(60) is formed is prepared. In the lower part and top of the metal film pattern, oxides locate. In the chip area, the electrolyte(112) is provided in order to be close with the task part of the metal film pattern. The electric resistance of the second between electrode which is close with the first electrode and electrolyte is measured at. The first electrode is electrically connected to the other part of the metal film pattern.
Abstract translation: 目的：晶片测试方法和晶片检测系统测量与电解质接近的电极之间的第二电极和与含有膜图案电气接近的第一电极的电阻。 了解腐蚀指标。 构成：制备包括其中形成有金属膜图案（60）的芯片区域的晶片（W）。 在金属膜图案的下部和顶部，氧化物定位。 在芯片区域中，提供电解质（112）以便与金属膜图案的任务部分接近。 测量与第一电极和电解质接近的电极之间的第二电极的电阻。 第一电极电连接到金属膜图案的另一部分。
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公开(公告)号：KR100734330B1
公开(公告)日：2007-07-02
申请号：KR1020060072264
申请日：2006-07-31
Applicant: 삼성전자주식회사
IPC: H01L21/304
Abstract: A method for drying a substrate and an apparatus for performing the same are provided to restrain a water spot and to prevent declination of a fine pattern by using a cleaning liquid containing deionized water and an organic fluoride based compound vapor. A substrate is cleaned by using a cleaning liquid containing deionized water and then rinsed by using a drying agent containing an organic fluoride based compound and alcohol(S10). An organic fluoride based compound vapor is supplied on to the rinsed substrate to form an organic fluoride base compound vapor atmosphere around the substrate, thereby removing the ionized water and the alcohol residing on the substrate(S20).
Abstract translation: 提供了一种用于干燥基板的方法和用于执行该方法的设备，以通过使用含有去离子水和有机氟化物基化合物蒸汽的清洁液来抑制水斑并防止精细图案的倾斜。 通过使用含有去离子水的清洁液来清洁基板，然后通过使用含有机氟化物基化合物和醇的干燥剂进行冲洗（S10）。 将有机氟化物基化合物蒸气供应到漂洗后的基板上以在基板周围形成有机氟化物基化合物蒸气气氛，由此除去沉积在基板上的离子化水和醇（S20）。
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Patent Agency Ranking
公开(公告)号：KR100734274B1
公开(公告)日：2007-07-02
申请号：KR1020050082450
申请日：2005-09-05
Applicant: 삼성전자주식회사
CPC classification number: H01L21/02071 , C11D3/042 , C11D3/046 , C11D3/2075 , C11D11/0047 , H01L21/0206 , H01L21/28282
Abstract: 본 발명은 플루오르 화합물, HNO
3 , 및 순수(deionized water)를 포함하는기판 세정용 조성물을 이용한 게이트 형성 방법을 개시한다. 상기 플루오르 화합물은 HF, NH
4 F 등을 포함할 수 있다. 상기 기판 세정용 조성물은 게이트 형성을 위한 금속막 식각에 의해 발생한 폴리머 부산물은 제거하고, 상기 폴리머 부산물 외의 막질은 잔류하도록 한다. 따라서 상기 기판 세정용 조성물을 이용하여 세정 공정을 행함으로써 전기적 특성이 우수한 반도체 소자의 게이트를 형성할 수 있다.
플루오르 화합물, HF, HNO3, 기판 세정용 조성물-
公开(公告)号：KR100673015B1
公开(公告)日：2007-01-24
申请号：KR1020050108694
申请日：2005-11-14
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242
CPC classification number: H01L28/91 , H01L21/31116 , H01L27/10817 , H01L27/10852
Abstract: A semiconductor device with a capacitor and a method of forming the same are provided to minimize the generation of bowing by using an improved process gas containing a main etching gas and a selectivity controlling gas. An etch stop layer(106) and a mold layer(108) are sequentially formed on a substrate(100). A mold electrode hole(110) for exposing a portion of the etch stop layer to the outside is formed on the resultant structure by patterning selectively the mold layer. A contact electrode hole(112) for exposing partially the substrate to the outside is formed through the etch stop layer by performing an isotropic dry etching process on the etch stop layer using a process gas containing a main etching gas and a selectivity controlling gas. A conductive layer is formed along an upper surface of the resultant structure.
Abstract translation: 提供具有电容器的半导体器件及其形成方法，以通过使用包含主蚀刻气体和选择性控制气体的改进的工艺气体来最小化弯曲的产生。 在衬底（100）上依次形成刻蚀停止层（106）和模具层（108）。 通过对成型层进行图案化，在所得到的结构上形成用于将蚀刻停止层的一部分暴露于外部的模具电极孔（110）。 通过使用含有主蚀刻气体和选择性控制气体的处理气体对蚀刻停止层进行各向同性干蚀刻工艺，通过蚀刻停止层，形成用于将衬底部分地暴露于外部的接触电极孔（112）。 沿所得结构的上表面形成导电层。
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公开(公告)号：KR100607176B1
公开(公告)日：2006-08-01
申请号：KR1020040020521
申请日：2004-03-25
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: H01L21/02052
Abstract: 희석 에이.피.엠 수용액(An Aqueous Solution Diluted Ammonia And Peroxide Mixture)을 이용한 반도체 장치의 제조방법들을 제공한다. 이 제조방법들은 실리콘-게르마늄의 합금막을 갖는 단결정 실리콘 기저판에 희석 에이.피.엠 수용액을 사용해서 개별 소자들의 특성을 향상시킬 수 있는 방안을 제시한다. 이를 위해서, 기저판의 주 표면 상에 적어도 일 회의 성장 공정을 통해서 합금막을 형성하고, 상기 성장 공정 후 합금막의 상면에 세정 공정을 실시한다. 이때에, 상기 세정 공정은 희석 APM(Ammonia and Peroxide Mixture) 수용액을 사용해서 실시하는데, 상기 희석 APM 수용액은 수산화 암모늄(NH
4 OH), 과수(H
2 O
2 ) 및 탈 이온수(DI-Water)의 체적 비율을 1: 0.5 ~ 20 : 300 ~ 2000 중의 선택된 비율을 사용해서 형성한다. 이를 통해서, 상기 희석 에이.피.엠 수용액을 이용한 반도체 장치는 실리콘-게르마늄의 합금막에 과도한 식각을 하지 않아서 단결정 실리콘 기저판 상부의 개별 소자들의 특성을 향상시킨다.
실리콘-게르마늄 합금막, 세정 공정, 희석 APM 수용액, 단결정 실리콘 기저판.-
公开(公告)号：KR1020030094688A
公开(公告)日：2003-12-18
申请号：KR1020020031942
申请日：2002-06-07
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: PURPOSE: A trench isolation method is provided to prevent the generation of seam or void by using a fluid insulation layer as a trench insulation layer, and to prevent recess in the trench insulation layer by eliminating a silicon nitride layer used as an etch stop layer through a selective dry etch process. CONSTITUTION: A mask layer pattern for defining an isolation region is formed on a substrate(102). The substrate is etched to form a trench by using the mask layer pattern as an etch mask. A fluid trench insulation layer(108) is formed in the trench and on the mask layer pattern. The trench insulation layer is planarized until the surface of the mask layer pattern is exposed. The mask layer pattern is removed through a selective dry etch process.
Abstract translation: 目的：提供沟槽隔离方法，以通过使用流体绝缘层作为沟槽绝缘层来防止接缝或空隙的产生，并且通过消除用作蚀刻停止层的氮化硅层来防止沟槽绝缘层中的凹陷 选择性干蚀刻工艺。 构成：在衬底（102）上形成用于限定隔离区域的掩模层图案。 通过使用掩模层图案作为蚀刻掩模来蚀刻衬底以形成沟槽。 在沟槽和掩模层图案上形成流体沟槽绝缘层（108）。 沟槽绝缘层被平坦化，直到掩模层图案的表面露出。 通过选择性干蚀刻工艺去除掩模层图案。
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公开(公告)号：KR102127644B1
公开(公告)日：2020-06-30
申请号：KR1020140070148
申请日：2014-06-10
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L21/31 , H01L21/324 , H01L29/78
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