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公开(公告)号：KR1020090004180A
公开(公告)日：2009-01-12
申请号：KR1020070068182
申请日：2007-07-06
Applicant: 시게이트 테크놀로지 엘엘씨 , 성균관대학교산학협력단
IPC: G03F7/00 , G11B5/86 , G03F1/50 , H01L21/027
CPC classification number: G03F7/0017 , G03F7/0002 , G03F7/0022 , G03F7/161 , G03F7/2012 , G11B5/865 , H01L21/0274 , H01L21/0337
Abstract: An anodized aluminum template, a method for preparing the anodized aluminum template, and a method for preparing a nanohole stamp by using the anodized aluminum template are provided to form the nanohole having the more regular arrangement. An anodized aluminum template(200) comprises an aluminum film(110); a guide line pattern which is formed on the aluminum film; and a porous aluminum oxide(120, 130) which is formed along the guide line pattern on the aluminum film and constitutes a plurality of nanoholes(h).
Abstract translation: 提供阳极氧化铝模板，用于制备阳极氧化铝模板的方法，以及通过使用阳极氧化铝模板制备纳米孔印模的方法，以形成具有更规则排列的纳米孔。 阳极氧化铝模板（200）包括铝膜（110）; 形成在铝膜上的引导线图案; 以及沿着铝膜上的引导线图案形成并构成多个纳米孔（h）的多孔氧化铝（120,130）。
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公开(公告)号：KR101434964B1
公开(公告)日：2014-08-29
申请号：KR1020130148443
申请日：2013-12-02
Applicant: 시게이트 테크놀로지 엘엘씨 , 성균관대학교산학협력단
Abstract: 양극 산화 알루미늄 템플릿 및 그 제조방법이 개시되어 있다. 개시된 양극 산화 알루미늄 템플릿은 알루미늄 막; 상기 알루미늄 막 위에 형성된 가이드 라인 패턴; 상기 알루미늄 막 위에 상기 가이드 라인 패턴을 따라 형성된 것으로, 복수의 나노홀을 이루는 다공성 산화 알루미늄;을 포함하는 것을 특징으로 하는 한다.
또한, 개시된 양극 산화 알루미늄 템플릿의 제조방법은 (가) 알루미늄 막을 교대 배치되는 제1영역과 제2영역으로 나누고, 상기 제1영역만을 1차 양극 산화 시키는 단계; (나) 상기 제1영역에 생성된 산화 알루미늄을 제거하는 단계; (다) 상기 알루미늄 막의 상기 제1영역 및 제2영역을 2차 양극 산화 시키는 단계;를 포함하는 것을 특징으로 한다.Abstract translation: 公开了一种阳极铝模板及其制造方法。 所公开的阳极铝模板包括铝膜; 在铝膜上形成的指导图案; 以及沿着引导线图案在铝膜上形成并构成多个纳米孔的多孔氧化铝。
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公开(公告)号：KR1020140009944A
公开(公告)日：2014-01-23
申请号：KR1020130148443
申请日：2013-12-02
Applicant: 시게이트 테크놀로지 엘엘씨 , 성균관대학교산학협력단
CPC classification number: G11B5/84 , G03F7/0002 , G03F7/0017
Abstract: Disclosed are an anodized aluminum template with the high degree of order and a manufacturing method thereof. The disclosed anodized aluminum template includes an aluminum film; a guide line pattern formed on the aluminum film; and a porous aluminum oxide which is formed on the aluminum film along the guide line pattern and which forms a plurality of nanoholes. Furthermore, a manufacturing method of the anodized aluminum template includes (a) a step of dividing the aluminum film into first and second regions which are alternately arranged and primarily anodizing first regions only; (b) a step of removing the aluminum oxide formed on the first regions; (c) and a step of secondarily anodizing the first and second regions of the aluminum film.
Abstract translation: 公开了一种高度顺序的阳极氧化铝模板及其制造方法。 所公开的阳极氧化铝模板包括铝膜; 形成在铝膜上的引导线图案; 以及多孔氧化铝，其沿着引导线图案形成在铝膜上并形成多个纳米孔。 此外，阳极氧化铝模板的制造方法包括（a）将铝膜分割成交替排列的第一和第二区域，并且主要仅阳极化第一区域的步骤; （b）除去形成在第一区域上的氧化铝的步骤; （c）和对铝膜的第一和第二区域进行二次阳极氧化的步骤。
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公开(公告)号：KR101250256B1
公开(公告)日：2013-04-03
申请号：KR1020110018777
申请日：2011-03-03
Applicant: 성균관대학교산학협력단
Abstract: 본 발명은 수직자기 기록매체의 자기기록층으로 사용되는 CoP 합금 박막을 제조하는 방법에 관한 것으로, 사카린(saccharine, C
7 H
5 NO
3 S)을 첨가한 도금용액에 시드층이 형성된 기판을 침지하고 전해 도금하다 상기 CoP 합금 박막을 형성하는 것을 특징으로 한다.
본 발명은, 전해도금 과정에서 첨가제를 첨가함으로써, 수직 이방성과 각형비가 크게 향상되어 수직자기 기록매체에 적용할 수 있는 CoP 합금 박막을 제조할 수 있는 효과가 있다.
또한, 본 발명의 제조방법으로 제조된 CoP 합금 박막은 재료비가 저렴하며 제조공정이 간단하여 수직자기 기록매체의 제조공정과 비용을 크게 낮출 수 있는 효과가 있다.-
公开(公告)号：KR101179386B1
公开(公告)日：2012-09-03
申请号：KR1020100032244
申请日：2010-04-08
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
CPC classification number: H01L21/50 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16146 , H01L2224/16235 , H01L2924/0001 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/19015 , H01L2924/19041 , Y10T436/170769 , H01L2224/13099
Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.
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Patent Agency Ranking
公开(公告)号：KR1020120010528A
公开(公告)日：2012-02-03
申请号：KR1020100072120
申请日：2010-07-26
Applicant: 성균관대학교산학협력단
IPC: H01L21/60
CPC classification number: H01L2224/11 , H01L2924/00012
Abstract: PURPOSE: A preparation method of a lead free solder bump using a sacrificial layer is provided to improve the mechanical reliability of a free lead solder bump which is formed finally by suppressing the growth of an inter metallic compound in the interface of copper post and a tin-based solder. CONSTITUTION: In a preparation method of a lead free solder bump using a sacrificial layer, a copper post(110) is formed on a substrate(100). A sacrificial layer(130) is formed on the copper post. The sacrificial layer is formed with a metal which is selected from palladium and a group which is formed with gold and platinum. A reflow process is performed after forming solder in the sacrificial layer. The solder is formed with a binary composite and or a ternary composite through electrolytic plating.
Abstract translation: 目的：提供一种使用牺牲层的无铅焊料凸块的制备方法，以提高自由铅焊料凸块的机械可靠性，最终通过抑制铜柱和锡的界面中的金属间化合物的生长而形成 的焊料。 构成：在使用牺牲层的无铅焊料凸块的制备方法中，在基板（100）上形成铜柱（110）。 牺牲层（130）形成在铜柱上。 牺牲层由选自钯和由金和铂形成的基团的金属形成。 在牺牲层中形成焊料之后进行回流工艺。 焊料通过电解电镀形成二元复合材料和/或三元复合材料。
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公开(公告)号：KR1020110129092A
公开(公告)日：2011-12-01
申请号：KR1020100048526
申请日：2010-05-25
Applicant: 성균관대학교산학협력단
Abstract: PURPOSE: A manufacturing method of a passive component embedded substrate is provided to manufacture an electronic product of an excellent structure with high reliability, thereby extending a lifespan of the electronic product and making a slimmer finished product. CONSTITUTION: A penetration hole(20) for embedding a passive component is arranged in a substrate. A via hole(10) for wiring is arranged in the substrate. The via hole for wiring is plated. A support stand is attached in one surface of the substrate. The passive component is embedded through the penetration hole. The wiring is arranged by plating the penetration hole for embedding the passive component.
Abstract translation: 目的：提供一种无源部件嵌入式基板的制造方法，以制造具有高可靠性的优异结构的电子产品，从而延长电子产品的寿命并制成更细的成品。 构成：用于嵌入无源部件的贯通孔（20）布置在基板中。 用于布线的通孔（10）设置在基板中。 接线用通孔进行电镀。 在基板的一个表面上附着支撑台。 被动部件通过穿透孔嵌入。 布线通过电镀用于嵌入被动元件的穿透孔而布置。
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公开(公告)号：KR1020110127513A
公开(公告)日：2011-11-25
申请号：KR1020100047043
申请日：2010-05-19
Applicant: 성균관대학교산학협력단
IPC: H01L23/488
CPC classification number: H01L2224/10
Abstract: PURPOSE: A method for manufacturing a silicon interposer is provided to easily form a solder bump by overcharging copper in the TSV(Through Silicon Via) of a substrate and projecting a copper post more than the substrate. CONSTITUTION: A TSV(Through Silicon Via)(130) is formed in a silicon substrate. An oxide film(140) and a copper seed layer(150) are formed in the silicon substrate in which the TSV is formed. A mask layer is formed in the upper side and the lower side of the silicon substrate. A copper post is formed to be dented more than a mask layer. One end of the cooper post is projected more than the silicon substrate by filling the copper in the TSV. Solder is deposited in one end of the copper post and the mask layer is removed. A solder bump is formed in one end of the copper post through a reflow process.
Abstract translation: 目的：提供一种用于制造硅插入件的方法，以便通过在基板的TSV（通过硅通孔）中对铜进行过充电而容易地形成焊料凸块，并将铜柱突出于基板以上。 构成：在硅衬底中形成TSV（硅通孔）（130）。 在形成TSV的硅衬底中形成氧化膜（140）和铜籽晶层（150）。 在硅衬底的上侧和下侧形成掩模层。 铜柱形成为比掩模层更凹陷。 通过在TSV中填充铜，铜柱的一端比硅衬底更突出。 在铜柱的一端沉积焊料，去除掩模层。 通过回流工艺在铜柱的一端形成焊料凸块。
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公开(公告)号：KR1020110112974A
公开(公告)日：2011-10-14
申请号：KR1020100032244
申请日：2010-04-08
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
CPC classification number: H01L21/50 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16146 , H01L2224/16235 , H01L2924/0001 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/19015 , H01L2924/19041 , Y10T436/170769 , H01L2224/13099
Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.
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公开(公告)号：KR1020110106184A
公开(公告)日：2011-09-28
申请号：KR1020100025448
申请日：2010-03-22
Applicant: 성균관대학교산학협력단
IPC: H05K9/00
Abstract: 본 발명은 동박 적층 필름 상에 포토리소그래피 공정을 통해 포토레지스트를 사용하여 도트 형태의 패턴을 형성하는 단계; 상기 동박 적층 필름 상에 형성된 도트 형태의 패턴에 연자성체를 도금하는 단계; 상기 연자성체를 도금한 후 포토레지스트를 제거하는 단계; 및 상기 단계를 거쳐 도트 형태로 연자성체가 도금된 동박 적층 필름의 구리층을 에칭액을 사용하여 에칭하는 단계를 포함하는 동박 적층 필름을 이용한 전자파 흡수시트의 제조방법에 관한 것이다. 본 발명은 전자파 흡수시트를 제조함에 있어 롤투롤 방식을 이용한 연속 제조 공정이 가능하며, 전자파 흡수시트를 플렉서블하고 현재 상용화된 제품에 비해 두께를 현저히 얇게 제조할 수 있는 동박 적층 필름을 이용한 전자파 흡수시트의 제조방법을 제공한다.
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