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公开(公告)号：KR101140349B1
公开(公告)日：2012-05-03
申请号：KR1020080090653
申请日：2008-09-16
Applicant: 한국전자통신연구원
Abstract: 본 발명에 따른 다단 연속 근사 레지스터 아날로그 디지털 변환기(Successive Approximation Register Analog Digital Converter)는 파이프라인 ADC와 유사한 수십 내지 수백 MHz 의 동작 속도를 유지하면서도 칩 면적과 전력소모를 줄일 수 있는 것을 특징으로 한다. 또한, 본 발명에 따른 아날로그 디지털 변환 방법은 다단으로 연결된 각 SAR ADC에서 동시 다발적으로 아날로그 디지털 변환이 이루어지므로, 아날로그 디지털 변환 시간을 줄일 수 있는 것을 특징으로 한다.
ADC, SAR(Successive Approximation Register), pipeline ADC-
公开(公告)号：KR1020110073173A
公开(公告)日：2011-06-29
申请号：KR1020100028448
申请日：2010-03-30
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A memory system comprising a plurality of DMA channels and an integrating management method for a plurality of DMA channels are provided to improve data transmission efficiency of a memory controller by the integrated management of multichannel memory controller and connected multiple DMA channels. CONSTITUTION: A memory controller(200) performs data transceiving operation with a memory(100). The memory controller comprises multiple channels which are physically separated each other. A DMA controller (300) is connected to the multiple channels of the memory controller and includes multiple DMA channels which are physically separated each other. The DMA controller performs data transceiving operation with the memory through the multiple DMA channels and the memory controller. An access module(400) connects the channels of the memory controller with the DMA channels each other.
Abstract translation: 目的：提供包括多个DMA通道的存储系统和用于多个DMA通道的集成管理方法，以通过多通道存储器控制器和连接的多个DMA通道的集成管理来提高存储器控制器的数据传输效率。 构成：存储器控制器（200）用存储器（100）执行数据收发操作。 存储器控制器包括物理上彼此分离的多个通道。 DMA控制器（300）连接到存储器控制器的多个通道，并且包括物理上彼此分离的多个DMA通道。 DMA控制器通过多个DMA通道和存储器控制器与存储器执行数据收发操作。 访问模块（400）将存储器控制器的通道与DMA通道相互连接。
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13.发明公开의사 차동 병합 커패시터 스위칭 디지털-아날로그 변환기 有权DAC（数字 - 模拟转换器）具有PSEUDO-DIFFERENTIAL MERGED-CAPACITOR SWITCHING METHOD
公开(公告)号：KR1020110015113A
公开(公告)日：2011-02-15
申请号：KR1020090072660
申请日：2009-08-07
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A pseudo-differential integrated capacitor switching digital-analog converter(DAC) is provided to maximize the capacitance of a capacitor unit by reducing the number of capacitors. CONSTITUTION: A sequential access DAC includes a positive DAC(200), a negative DAC(100), a comparator(300), and a logic part(400). The structures of the negative DAC and the positive DAC are identical. The negative DAC and the positive DAC respectively includes four bits, one coupling capacitor, and four switching elements. A bit capacitor is in connection with the input terminal of the comparator.
Abstract translation: 目的：提供一个伪差分集成电容切换数模转换器（DAC），通过减少电容器的数量来最大化电容器单元的电容。 构成：顺序访问DAC包括正DAC（200），负DAC（100），比较器（300）和逻辑部分（400）。 负DAC和正DAC的结构是相同的。 负DAC和正DAC分别包括四位，一个耦合电容和四个开关元件。 一个位电容与比较器的输入端相连。
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公开(公告)号：KR1020110011533A
公开(公告)日：2011-02-08
申请号：KR1020100056982
申请日：2010-06-16
Applicant: 한국전자통신연구원
Abstract: PURPOSE: An absolute difference operation device is provided to use one adder and one comparator, thereby performing absolute difference operation with a low logic surface load. CONSTITUTION: A comparator(410) compares the size between two integers. According to the comparing result, the first and the second selectors(420,430) respectively select/output one among two integers. An inverter(440) mending-process a selection result value of the second selector. An adder(450) adds 1 and a value which is mending-processes by the inverter and the selection result value of the first selector.
Abstract translation: 目的：提供绝对差分运算器件，使用一个加法器和一个比较器，从而在低逻辑表面负载下执行绝对差运算。 构成：比较器（410）比较两个整数之间的大小。 根据比较结果，第一和第二选择器（420,430）分别选择/输出两个整数之一。 逆变器（440）对第二选择器的选择结果值进行修补处理。 加法器（450）将反相器进行修补处理的值和第一选择器的选择结果值相加1。
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公开(公告)号：KR1020110011532A
公开(公告)日：2011-02-08
申请号：KR1020100056911
申请日：2010-06-16
Applicant: 한국전자통신연구원
CPC classification number: H03M3/32 , H03M3/39 , H03M2201/62 , H03M2201/932
Abstract: PURPOSE: An active type RC integrator and a continuous time sigma-delta modulator are provided to improve the gain of an active type RC integrator by turning on a switch. CONSTITUTION: A first base resistor(RBASE1) is connected between a first input node and the positive input terminal of an amplifier. A second base resistor(RBASE2) is connected between a second input node and the negative input terminal of the amplifier. A first resistor part(1) is connected between the second input node and the positive input terminal of the amplifier. A second resistor part(2) is connected between the first input node and the negative input terminal of the amplifier. A first switch(SWDUM1) switches on and off the first base resistor. A second switch(SWDUM2) switches on and off the second base resistor. The gain of an input signal is controlled according to the input resistance varied by the first resistor part and the second resistor part.
Abstract translation: 目的：提供有源型RC积分器和连续时间Σ-Δ调制器，通过开启开关来提高有源型RC积分器的增益。 构成：第一个基极电阻（RBASE1）连接在放大器的第一个输入节点和正极输入端子之间。 第二基极电阻（RBASE2）连接在放大器的第二输入节点和负输入端之间。 第一电阻器部分（1）连接在第二输入节点和放大器的正输入端之间。 第二电阻器部分（2）连接在放大器的第一输入节点和负输入端之间。 第一开关（SWDUM1）打开和关闭第一个基极电阻。 第二个开关（SWDUM2）打开和关闭第二个基极电阻。 根据由第一电阻器部件和第二电阻器部件变化的输入电阻来控制输入信号的增益。
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Patent Agency Ranking
公开(公告)号：KR1020110011528A
公开(公告)日：2011-02-08
申请号：KR1020100052154
申请日：2010-06-03
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A DMA controller with an interrupt control processor is provided to reduce interrupt control load of a main processors. CONSTITUTION: A DMA(Direct Memory Access) channel register bank(240) stores a DMA channel operation request and a DMA set point. An interrupt control processor(250) performs a control program stored in a program memory(220). A DMA channel control module(270) controls operation of a DMA channel(150) according to the DMA set value by responding to a DMA channel activation command. An interrupt/DMA request and cancel module(260) generates a release signal about an interrupt processed by the interrupt control processor.
Abstract translation: 目的：提供具有中断控制处理器的DMA控制器，以减少主处理器的中断控制负载。 构成：DMA（直接存储器访问）通道寄存器组（240）存储DMA通道操作请求和DMA设定点。 中断控制处理器（250）执行存储在程序存储器（220）中的控制程序。 DMA通道控制模块（270）通过响应DMA通道激活命令，根据DMA设定值来控制DMA通道（150）的操作。 中断/ DMA请求和取消模块（260）产生关于由中断控制处理器处理的中断的释放信号。
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公开(公告)号：KR1020110011512A
公开(公告)日：2011-02-08
申请号：KR1020100021678
申请日：2010-03-11
Applicant: 한국전자통신연구원
CPC classification number: H03B5/1296 , H03B5/1215 , H03B5/1218 , H03B5/1228 , H03B5/1246 , H03B2200/009 , H03B2201/036
Abstract: PURPOSE: A voltage controlled generator is provided to operate in a differential mode and a common mode by independently connecting a complementary active circuit element to both sides of a resonant unit. CONSTITUTION: A first oscillator comprises transistors(M5-M8) such as a complementary active element connected to both ends of a resonant unit(60) of a transformer base through an N-PMOS cross-connection structure. A second oscillator comprises transistors(M1-M4) such as a complementary active element connected to both ends of a resonant unit(60) of a transformer base through a gate coupling structure. A double band voltage controlled oscillator is formed by binding the first and second oscillators.
Abstract translation: 目的：通过独立地将互补有源电路元件连接到谐振单元的两侧，提供电压发生器以在差模和共模下工作。 构成：第一振荡器包括通过N-PMOS交叉连接结构连接到变压器基座的谐振单元（60）两端的互补有源元件的晶体管（M5-M8）。 第二振荡器包括通过栅极耦合结构连接到变压器基座的谐振单元（60）两端的互补有源元件的晶体管（M1-M4）。 通过结合第一和第二振荡器形成双频带压控振荡器。
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公开(公告)号：KR100981732B1
公开(公告)日：2010-09-13
申请号：KR1020080085999
申请日：2008-09-01
Applicant: 한국전자통신연구원
IPC: G05F3/24
CPC classification number: G05F3/30
Abstract: 본 발명은 밴드갭 기준전압 발생기에 관한 것으로, 제1, 2 바이폴라 트랜지스터에 제4, 5 NMOS 트랜지스터를 병렬로 각각 연결하여 절대온도에 반비례하는 CTAT(Complementary To Absolute temperature) 전압이 상기 제5 NMOS 트랜지스터의 문턱전압 만큼 감소되도록 한 것을 특징으로 한다. 따라서, 본 발명에 따르면, 절대온도에 비례하는 PTAT(Proportional To Absolute Temperature) 전압의 온도 계수에 대한 가중치값이 감소되어 제로의 온도 계수를 위한 저항비를 1/2 정도로 줄일 수 있으므로 밴드갭 기준전압 발생기의 소형화를 도모할 수 있다. 또한, 상기 제1, 2 바이폴라 트랜지스터에 병렬로 각각 연결된 제2, 3 저항에 의해 1V 이하의 안정된 기준전압을 제공할 수 있다.
저전압, 기준전압, 트랜지스터, 저항, 온도 계수, 가중치-
公开(公告)号：KR1020100073948A
公开(公告)日：2010-07-01
申请号：KR1020090026593
申请日：2009-03-27
Applicant: 한국전자통신연구원
IPC: H03B5/24
CPC classification number: H03K3/0231 , H03B2201/0208 , H03K3/0322 , H03K5/135
Abstract: PURPOSE: A ring oscillator with a broadband output frequency is provided to simply change an oscillation frequency by controlling a control signal applied to the varactor. CONSTITUTION: Each delay cell comprises a transconductance unit(210), a reverse speed varying unit(230), and an output speed varying unit(270). The transconductance unit outputs a signal delayed for a preset time to first and second output nodes by reversing a first differential input signal of the delay cell. The reverse speed varying unit is connected to the transconductance unit. The reverse speed varying unit varies the revere speed of the first differential input signal according to the first control signal. An active load unit provides an active load to the transconductance unit by receiving a second differential input signal from the delay cell before two stages. The output speed varying unit varies the output speed of the differential output signal from the transconductance unit according to a second control signal.
Abstract translation: 目的：提供具有宽带输出频率的环形振荡器，通过控制施加到变容二极管的控制信号来简单地改变振荡频率。 构成：每个延迟单元包括跨导单元（210），反向速度变化单元（230）和输出速度变化单元（270）。 跨导单元通过反转延迟单元的第一差分输入信号来输出延迟预设时间的信号到第一和第二输出节点。 反转速度变化单元连接到跨导单元。 反转速度变化单元根据第一控制信号改变第一差分输入信号的转向速度。 有源负载单元通过在两级之前从延迟单元接收第二差分输入信号来向跨导单元提供有源负载。 输出速度变化单元根据第二控制信号改变来自跨导单元的差分输出信号的输出速度。
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公开(公告)号：KR1020100070978A
公开(公告)日：2010-06-28
申请号：KR1020090071284
申请日：2009-08-03
CPC classification number: H03L7/0898 , H03B5/24 , H03L7/099 , H03L7/18
Abstract: PURPOSE: A low voltage frequency synthesizer is provided to prevent performance deterioration caused by a broadband, low phase noise, external environment, and process deviation by supplying the supply power of a charge pump from a voltage-controlled oscillator. CONSTITUTION: A frequency/phase detector(140) receives and compares a reference frequency and a feedback frequency and outputs comparison signal. A charge pump(110) receives the comparison signal and outputs a current that corresponds to the comparison signal. A low band pass filter(120) generates a voltage in correspondence to the output current of the charge pump. A voltage-controlled oscillator receives the message of the low band pass filter. A DC voltage converter(150) receives the boosting voltage of the voltage-controlled oscillator.
Abstract translation: 目的：提供低压频率合成器，通过从压控振荡器提供电荷泵的电源，防止宽带，低相位噪声，外部环境和工艺偏差引起的性能恶化。 构成：频率/相位检测器（140）接收并比较参考频率和反馈频率并输出比较信号。 电荷泵（110）接收比较信号并输出对应于比较信号的电流。 低通滤波器（120）产生对应于电荷泵的输出电流的电压。 压控振荡器接收低通滤波器的消息。 直流电压转换器（150）接收压控振荡器的升压电压。
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