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公开(公告)号：KR1020130067612A
公开(公告)日：2013-06-25
申请号：KR1020110134351
申请日：2011-12-14
Applicant: 한국전자통신연구원
CPC classification number: G06K9/6269 , G06K9/4614 , G06T7/00
Abstract: PURPOSE: A feature vector classification device and a recognition device using the same are provided to reduce a running time and size of hardware in a process of feature vector extraction and classification. CONSTITUTION: A feature vector extractor(10) generates and extracts a feature vector and a normalized value from an inputted image. A feature vector classifier(20) normalizes the feature vector based on the normalized value and recognizes the inputted image through classification of the normalized feature vector. A search window inputted in a recognition device(1) is classified according to an index of the classified feature vector. [Reference numerals] (10) Feature vector extractor; (20) Feature vector classifier; (AA) Searching window; (BB) Feature vector
Abstract translation: 目的：提供特征向量分类装置和使用该特征向量分类装置的识别装置，以在特征向量提取和分类过程中减少硬件的运行时间和大小。 构成：特征向量提取器（10）从输入图像生成并提取特征向量和归一化值。 特征向量分类器（20）基于归一化值对特征向量进行归一化，并通过归一化特征向量的分类来识别输入的图像。 输入到识别装置（1）中的搜索窗口根据分类的特征向量的索引进行分类。 （附图标记）（10）特征向量提取器; （20）特征向量分类器; （AA）搜索窗口; （BB）特征向量
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公开(公告)号：KR1020120032897A
公开(公告)日：2012-04-06
申请号：KR1020100094451
申请日：2010-09-29
Applicant: 한국전자통신연구원 , 안동대학교 산학협력단
IPC: G06T7/00
CPC classification number: G06K9/3241 , G06K9/4642 , G06K9/6256
Abstract: PURPOSE: A method for detecting an entity and a system thereof are provided to perform an entity detection algorithm in the remaining areas excluding the area in which a target detection object does not exist. CONSTITUTION: An image is inputted to an entity detection system(S410). The entity detection system extracts a search area for the image(S420). When the search area has been extracted, the entity detection system extracts feature data from the image(S430). After extracting the feature data, the entity detection system finally detects an entity through a boosting classifier based model such as Adaboost algorithm, and so on(S440).
Abstract translation: 目的：提供一种用于检测实体的方法及其系统，以在除了目标检测对象不存在的区域之外的剩余区域中执行实体检测算法。 构成：将图像输入到实体检测系统（S410）。 实体检测系统提取图像的搜索区域（S420）。 当提取搜索区域时，实体检测系统从图像中提取特征数据（S430）。 提取特征数据后，实体检测系统最终通过基于提升分类器的Adaboost算法等进行实体检测（S440）。
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公开(公告)号：KR100960148B1
公开(公告)日：2010-05-27
申请号：KR1020080042497
申请日：2008-05-07
Applicant: 한국전자통신연구원
CPC classification number: G06F9/3001 , G06F9/30189 , G06F9/3802 , G06F9/3885
Abstract: 데이터 프로세싱 회로는, 동작 제어 신호 및 메모리 제어 신호를 출력하는 제어 유닛과, 각각이 상기 메모리 제어 신호에 응답해서 명령을 출력하는 복수의 프로그램 메모리들, 그리고 각각이 상기 동작 제어 신호에 응답해서 상기 복수의 프로그램 메모리들로부터의 명령들 중 어느 하나를 선택적으로 수행하는 연산기들을 포함하여 동작 환경에 따라서 유연하게 동작 모드 변환이 가능하다.
Abstract translation: 数据处理电路包括：控制单元，用于输出操作控制信号和存储器控制信号;多个程序存储器，每个用于响应于存储器控制信号输出命令; 以及一个操作单元，用于有选择地从多个程序存储器的程序存储器中执行任何一个指令。
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公开(公告)号：KR1020090116511A
公开(公告)日：2009-11-11
申请号：KR1020080042497
申请日：2008-05-07
Applicant: 한국전자통신연구원
CPC classification number: G06F9/3001 , G06F9/30189 , G06F9/3802 , G06F9/3885
Abstract: PURPOSE: A data processing circuit is provided to convert efficiently an operating mode according to the operating environment by implementing a multi-mode of a parallel processing. CONSTITUTION: A control unit(110) outputs the operating control signal and memory control signal. Program memories(121-123) output a command in response to the memory control signal. Computing units(131-133) respond to the operating control signal and selectively perform one command among the program memories. The operating control signal outputted from the control unit includes SIMD mode signal and memory selection control signal on SIMD(Single Instruction stream Multiple Data stream) mode.
Abstract translation: 目的：提供数据处理电路，通过实现并行处理的多模式，根据操作环境有效地转换操作模式。 构成：控制单元（110）输出操作控制信号和存储器控制信号。 程序存储器（121-123）响应于存储器控制信号输出命令。 计算单元（131-133）响应于操作控制信号，并且在程序存储器中选择性地执行一个命令。 从控制单元输出的操作控制信号包括SIMD（单指令流多数据流）模式下的SIMD模式信号和存储器选择控制信号。
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公开(公告)号：KR1020090065274A
公开(公告)日：2009-06-22
申请号：KR1020070132760
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: G06F15/78
Abstract: A reconfigurable SoC(System on Chip) system and a method of implementing the same are provided to perform dynamic reconfiguration by operating based on the automatic sensing of an IP necessary for the reconfiguration of an SoC. A flash memory(130) stores plural IPs(Internet Protocols), and an intrinsic code detecting unit(120) detects the intrinsic code of an IP called from a system software(110). A reconfigurable SoC(140) has a processor. The reconfigurable SoC unit configures an SoC by reading out an IP corresponding to the sensed intrinsic code.
Abstract translation: 提供了可重新配置的SoC（片上系统）系统及其实现方法，以通过基于对SoC的重新配置所需的IP的自动感测进行操作来执行动态重新配置。 闪存（130）存储多个IP（互联网协议），并且内部代码检测单元（120）检测从系统软件（110）调用的IP的固有代码。 可重新配置的SoC（140）具有处理器。 可重新配置的SoC单元通过读出对应于感测到的内在代码的IP来配置SoC。
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Patent Agency Ranking
公开(公告)号：KR100896269B1
公开(公告)日：2009-05-08
申请号：KR1020070054309
申请日：2007-06-04
Applicant: 한국전자통신연구원
CPC classification number: G06F9/30036
Abstract: 본 발명은 SIMD 병렬 프로세서에 관한 것으로, SIMD 병렬 프로세서는 명령어 레지스터, 명령어 디코더, 레지스터 파일 선택 회로, 및 레지스터 파일을 포함하며, 명령어에 의하여 SIMD 동작, SISD 동작, Row 동작, 또는 Column 동작에 필요한 레지스터 파일의 데이터를 선택적으로 제어함으로써 응용에 따라서 SIMD 동작, SISD 동작, Row 동작, 및 Column 동작 중 어느 하나의 동작을 수행한다. 본 발명에 의하면, 활용도, 효율도 및 유연성이 뛰어난 SIMD 병렬 프로세서를 구현할 수 있다.
병렬 프로세서, SIMD, 레지스터 파일, 명령어(instruction)-
公开(公告)号：KR1020080052225A
公开(公告)日：2008-06-11
申请号：KR1020070054320
申请日：2007-06-04
Applicant: 한국전자통신연구원
IPC: H03K19/094
CPC classification number: H03K3/356147 , H03K3/012 , H03K3/356156
Abstract: A low power clock gating circuit is provided to realize a high speed and low power by using a low threshold voltage device and a high threshold voltage device, respectively. A low power clock gating circuit(450) comprises PMOS transistors and NMOS transistors. The PMOS transistors are electrically connected between a power terminal and a first inverter(402), between the power terminal and a second inverter(422), and between the power terminal and an end gate(444), respectively. The PMOS transistors are controlled by a sleep controlling signal applied through a sleep controlling terminal and have a high threshold voltage. The NMOS transistors are electrically connected between a ground and the first inverter, between the ground and the second inverter, and between the ground and the end gate, respectively. The NMOS transistors are controlled by the sleep controlling signal and have a high threshold voltage.
Abstract translation: 提供了一种低功率时钟选通电路，通过分别使用低阈值电压器件和高阈值电压器件来实现高速和低功耗。 低功率时钟选通电路（450）包括PMOS晶体管和NMOS晶体管。 PMOS晶体管分别电连接在电源端子和第一逆变器（402）之间，电源端子与第二反相器（422）之间，以及电源端子与端口（444）之间。 PMOS晶体管由通过睡眠控制端子施加的睡眠控制信号控制并且具有高阈值电压。 NMOS晶体管分别电连接在接地和第一反相器之间，接地与第二反相器之间，以及地与端口之间。 NMOS晶体管由睡眠控制信号控制并具有高阈值电压。
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公开(公告)号：KR101725126B1
公开(公告)日：2017-04-12
申请号：KR1020110134351
申请日：2011-12-14
Applicant: 한국전자통신연구원
CPC classification number: G06K9/6269
Abstract: 본발명은특징벡터추출기및 이를이용하는인식장치에대한것이다. 본발명의실시예에의한인식장치는특징벡터및 정규화값을출력하는특징벡터추출기및 상기특징벡터추출기로부터입력된상기특징벡터를상기정규화값을기초로정규화한뒤 상기특징벡터를분류하는특징벡터분류기를포함한다. 따라서본 발명의특징벡터추출기및 이를이용하는인식장치는특징벡터추출및 분류과정에있어서, 수행시간및 그에요구되는하드웨어의크기가감소된다.
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