公开(公告)号：GB2599523B

公开(公告)日：2022-12-28

申请号：GB202117805

申请日：2020-04-06

Applicant: IBM

Inventor： ALEXANDER REZNICEK ,  JENG-BANG YAU ,  BAHMAN HEKMATSHOARTABARI

IPC: G01N27/414 ,  H01L29/73

Abstract: A biosensor includes a bulk silicon substrate and a vertical bipolar junction transistor (BJT) formed on at least a portion of the substrate. The BJT includes an emitter region, a collector region and an epitaxially grown intrinsic base region between the emitter and collector regions. The biosensor further includes a sensing structure formed on at least a portion of two vertical surfaces of the intrinsic base region of the BJT. The sensing structure includes a channel/trench opening, exposing the intrinsic base region on at least first and second opposing sides thereof, and at least one dielectric layer formed in the channel/trench opening and contacting at least a portion of the intrinsic base region, the dielectric layer being configured to respond to charges in biological molecules.

公开(公告)号：IL297512A

公开(公告)日：2022-12-01

申请号：IL29751222

申请日：2022-10-20

Applicant: IBM ,  ALEXANDER REZNICEK ,  BAHMAN HEKMATSHOARTABARI ,  KARTHIK BALAKRISHNAN

Inventor： ALEXANDER REZNICEK ,  BAHMAN HEKMATSHOARTABARI ,  KARTHIK BALAKRISHNAN

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861

Abstract: One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source/drain (S/D) is disposed on the substrate. The first (second) S/D has a first (second) S/D doping concentration with a first (second) S/D doping type. One or more p-n junctions form one or more respective diodes. There is a first side and a second side of each of the p-n junctions. The first (second) sides of the p-n junctions electrically and physically connect to the first (second) S/Ds and have the same type of doping, respectively. A gate stack, made of a gate dielectric layer and a gate metal, interfaces and surrounds each of the p-n junctions.

公开(公告)号：GB2603684A

公开(公告)日：2022-08-10

申请号：GB202204972

申请日：2020-09-22

Applicant: IBM

Inventor： ALEXANDER REZNICEK ,  DEVIKA SIL ,  OLEG GLUSCHENKOV ,  YASIR SULEHRIA

IPC: H01L43/02 ,  H01L43/08

Abstract: A hardened gap fill dielectric material that has improved chemical and physical properties is formed laterally adjacent to a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode structure of a memory structure. The harden gap fill dielectric material can be formed by introducing, via ion implantation, a bond breaking additive into an as deposited gap fill dielectric material layer and thereafter curing the gap fill dielectric material layer containing the bond breaking additive. The curing includes UV curing alone, or UV curing in combination with laser annealing. The curing employed in the present application does not negatively impact the MTJ pillar or top electrode structure.

公开(公告)号：GB2635303A

公开(公告)日：2025-05-07

申请号：GB202503721

申请日：2023-09-07

Applicant: IBM

Inventor： POUYA HASHEMI ,  ALEXANDER REZNICEK

IPC: H10N50/10 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device and methods forming the device is disclosed. The semiconductor device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode (136,236) on the MTJ stack. At least one of the bottom electrode and the top electrode (136,236) includes doped SiGeSn.

公开(公告)号：IL298029B1

公开(公告)日：2025-05-01

申请号：IL29802922

申请日：2022-11-07

Applicant: IBM CORP ,  TAO LI ,  TSUNG SHENG KANG ,  RUILONG XIE ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV

Inventor： TAO LI ,  TSUNG-SHENG KANG ,  RUILONG XIE ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D64/23 ,  H10D64/62

Abstract: Semiconductor device designs having a buried power rail with a sloped epitaxy buried contact are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate, wherein at least one of the source and drains has a sloped surface; a buried power rail embedded in the substrate; and a buried contact that connects the buried power rail to the sloped surface of the at least one source and drain. Sidewall spacers separate the buried power rail from the substrate. A top of the sloped surface of the at least one source and drain is above a top surface of the buried contact. Methods of forming a semiconductor FET device are also provided.

公开(公告)号：GB2606919B

公开(公告)日：2025-04-16

申请号：GB202209965

申请日：2020-12-14

Applicant: IBM

Inventor： TAKASHI ANDO ,  RUILONG XIE ,  POUYA HASHEMI ,  ALEXANDER REZNICEK

IPC: H10N70/00 ,  H10N70/20

Abstract: A resistive random access memory (RRAM) structure includes top and bottom electrodes electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material is disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable change in resistance under influence of at least an electric field and/or heat. Dielectric spacers are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacers and covering at least a portion of sidewalls of the top electrode. The passivation layer is self-aligned with the first metal connection line.

公开(公告)号：GB2607792B

公开(公告)日：2024-12-18

申请号：GB202212342

申请日：2021-01-05

Applicant: IBM

Inventor： ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV ,  YASIR SULEHRIA ,  DEVIKA SIL

IPC: H10N50/01

Abstract: Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.

公开(公告)号：GB2607740A

公开(公告)日：2022-12-14

申请号：GB202209975

申请日：2020-12-04

Applicant: IBM

Inventor： ALEXANDER REZNICEK ,  BAHMAN HEKMATSHOARTABARI ,  TAKASHI ANDO ,  KARTHIK BALAKRISHNAN

IPC: H01L27/24

Abstract: A one-transistor-two-resistor (1T2R) resistive random access memory (ReRAM) structure, and a method for forming the same, includes forming a vertical field effect transistor (VFET) including an epitaxial region (810) located above a channel region (502) and below a dielectric cap (708). The epitaxial region (810) includes two opposing protruding regions of triangular shape bounded by planes that extend horizontally beyond the channel region (502). A ReRAM stack is conformally deposited on the VFET. The ReRAM stack includes an oxide layer (1910) located directly above the epitaxial region (810), a top electrode layer (1912) directly above the oxide layer (1910) and a metal fill (1920) above the top electrode layer (1912). Each of the two opposing protruding regions of the epitaxial region (810) acts as a bottom electrode for the ReRAM stack.

公开(公告)号：GB2605327A

公开(公告)日：2022-09-28

申请号：GB202208675

申请日：2020-12-04

Applicant: IBM

Inventor： ALEXANDER REZNICEK ,  BAHMAN HEKMATSHOARTABARI ,  TAKASHI ANDO

IPC: H01L29/66

Abstract: A two-transistor-two-resistor (2T2R) resistive random access memory (ReRAM) structure, and a method for forming the same includes two vertical field effect transistors (VFETs) formed on a substrate (102), each VFET includes an epitaxial region (410) located above a channel region (302) and below a dielectric cap(308). The epitaxial region (410) includes two opposing protruding regions of triangular shape that extend horizontally beyond the channel region (302). A metal gate material (602) is disposed on and around the channel region (302). A portion of the metal gate material (602) is located between the two VFETs. A ReRAM stack is deposited within two openings (1010) adjacent to a side of each VFET that is opposing the portion of the metal gate material (602) located between the two VFETs. A portion of the epitaxial region (410) in direct contact with the ReRAM stack acts as a bottom electrode for the ReRAM structure.

公开(公告)号：GB2550740A

公开(公告)日：2017-11-29

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer(20) disposed on a substrate(10), a silicon germanium layer(30) disposed on the dielectric layer(20), and a strained semiconductor material layer(40) disposed directly on the silicon germanium layer(30), forming a plurality of fins(43, 45) on the SSOI structure, forming a gate structure(50) over a portion of at least one fin in a nFET region, forming a gate structure(60) over a portion of at least one fin in a pFET region, removing the gate structure(60) over the portion of the at least one fin in the pFET region, removing the silicon germanium layer(30) exposed by the removing, and forming a new gate structure(90) over the portion of the at least one fin in the pFET region, such that the new gate structure(90) surrounds the portion on all four sides.