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    High bandwidth dram with low operating power modes
    15.
    发明专利
    High bandwidth dram with low operating power modes 未知

    公开(公告)号：SG77255A1

    公开(公告)日：2000-12-19

    申请号：SG1999003392

    申请日：1999-07-15

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  KELLOGG MARK WILLIAM ,  HEDBERG ERIK L ,  DELL TIMOTHY JAY

    IPC: G06F13/16 ,  G06F13/38 ,  H01L21/8242

    Abstract: A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.

    16.
    发明专利
    未知

    公开(公告)号：ES2135507T3

    公开(公告)日：1999-11-01

    申请号：ES94108520

    申请日：1994-06-03

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  FARRAR SR PAUL ALDEN ,  HOWELL WAYNE JOHN ,  MILLER CHRISTOPHER PAUL ,  PERLMAN DAVID JACOB

    IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

    Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

    17.
    发明专利
    未知

    公开(公告)号：DE69420201T2

    公开(公告)日：2000-03-23

    申请号：DE69420201

    申请日：1994-06-03

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  FARRAR SR ,  HOWELL WAYNE JOHN ,  MILLER CHRISTOPHER PAUL ,  PERLMAN DAVID JACOB

    IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

    Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

    18.
    发明专利
    未知

    公开(公告)号：DE69420201D1

    公开(公告)日：1999-09-30

    申请号：DE69420201

    申请日：1994-06-03

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  FARRAR SR ,  HOWELL WAYNE JOHN ,  MILLER CHRISTOPHER PAUL ,  PERLMAN DAVID JACOB

    IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

    Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

    19.
    发明专利
    未知

    公开(公告)号：AT183851T

    公开(公告)日：1999-09-15

    申请号：AT94108520

    申请日：1994-06-03

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  FARRAR SR PAUL ALDEN ,  HOWELL WAYNE JOHN ,  MILLER CHRISTOPHER PAUL ,  PERLMAN DAVID JACOB

    IPC: H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

    Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

    Integrated high-performance decoupling capacitor
    20.
    发明专利
    Integrated high-performance decoupling capacitor 未知

    公开(公告)号：SG66413A1

    公开(公告)日：1999-07-20

    申请号：SG1997004090

    申请日：1997-11-19

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  HOWELL WAYNE JOHN ,  TONTI WILLIAM ROBERT PATRICK ,  ZALESNSKI JERZY MARIA

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L23/522 ,  H01L29/92 ,  H01L21/76

    Abstract: An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance. Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip. Very precise decoupling of selected areas in the chip circuit can be achieved by forming precise and multiple metal deposits of either the same size or of varying sizes to define specific capacitances and individually connecting these deposits to the circuit areas needing the precise decoupling capacitance.

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