公开(公告)号：JP2002215706A

公开(公告)日：2002-08-02

申请号：JP2001338435

申请日：2001-11-02

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  HATHAWAY DAVID J ,  LACKEY DAVID E ,  LEPSIC THOMAS M ,  LICHTENSTEIGER SUSAN K ,  TETREAULT SCOTT A ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a logical and physical constitution for a voltage island. SOLUTION: In design of a semiconductor chip, it is parted by the unit of bin, which means plural ranges in the design. Design of one semiconductor chip can thus be sliced to various ranges, and these ranges can be allotted to various voltage levels. Each bin can be regarded as one voltage island. Circuits in the design can be added to various bins, or eliminated from the various bins. Circuit speed and power can be increased or reduced by this. When the circuit is disposed in the bin to which a high voltage is allotted, speed and power are increased. When the circuit is disposed in the bin having a low voltage, speed and power are reduced. The size and position of the bin can also be changed. By repeating these steps, the optimum power consumption can be achieved while satisfying other standards such as constraint related to speed.

公开(公告)号：JP2002328962A

公开(公告)日：2002-11-15

申请号：JP2002031625

申请日：2002-02-08

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  AMIR H FARRAHI ,  HATHAWAY DAVID J ,  THOMAS M RESHIKKU ,  JAGANATHAN NAGASHIMAAN ,  SCOTT A TETORAATO ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure which reduces power consumption on a microelectronic circuit. SOLUTION: This method distinguishes at least one wiring pair including the first wiring and the second wiring. The second wiring is already tristated or tristatable. The wiring pair has same directional probability over the prescribed or the user selected minimum same directional switching availability for one clock cycle. Or, the wiring pair has opposite directional probability over the prescribed or the user selected minimum opposite directional switching availability for one clock cycle. The first and the second wiring satisfies at least one mathematical relation, and this mathematical relation includes distance between the first and the second wiring, and common run length of the first and the second wiring.

公开(公告)号：JP2002230066A

公开(公告)日：2002-08-16

申请号：JP2001369057

申请日：2001-12-03

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  HATHAWAY DAVID J ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  G06F1/32

Abstract: PROBLEM TO BE SOLVED: To provide a logic system designing method for reducing leak by forcing the sate of a logical gate based on probabilistic analysis. SOLUTION: This method for reducing the leak power of a logical network comprises a step for identifying the 'sleep state' of each net by using observability don't care information, a step for determing at least one net in which expected power consumption is reduced by forcing a net to a specific value during at least a part of the sleep state based on probabilistic analysis, and a step for forcing the determined net to the determined value during the determined part of the sleep state.

公开(公告)号：JP2007158340A

公开(公告)日：2007-06-21

申请号：JP2006326345

申请日：2006-12-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHN JOHN M ,  HIBBELER JASON D ,  TELLEZ GUSTAVO E

IPC: H01L21/82 ,  G06F17/50

CPC classification number: G06F17/5077

Abstract: PROBLEM TO BE SOLVED: To provide the method of implementing yield recognition IC route specification for designing, and to provide a computer program.
SOLUTION: In this method, an early global routing for satisfying wiring congestion constraint is implemented. Then, in this method, wire spreading and wire widening are implemented per layer with respect to global routing, based on, for example, the second congestion optimization. Subsequently, the timing convergence is implemented for global routing by using the result of wire spreading and wire widening. Then, the adjustment of wiring width after routing and wire spreading is carried out by using a critical area yield model. Furthermore, this method enables optimization of already routed data.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供实现产量识别IC路由规范的设计方法，并提供计算机程序。 解决方案：在这种方法中，实现了用于满足布线拥塞约束的早期全局路由。 然后，在这种方法中，基于例如第二拥塞优化，相对于全局路由，每层实施有线扩展和线拓宽。 随后，通过使用线扩展和线宽扩展的结果，实现了全局路由的定时收敛。 然后，通过使用临界区域产量模型来进行布线和布线扩展之后的布线宽度的调整。 此外，该方法能够优化已经路由的数据。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002288253A

公开(公告)日：2002-10-04

申请号：JP2002004163

申请日：2002-01-11

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  COHN JOHN M ,  NEVES JOSE L P

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a method for adding decoupling capacitance which is installed within an integrated circuit between two-dimensional design stages of the integrated circuit. SOLUTION: In the method for adding decoupling capacitance in the integrated circuit design, a step for forming a two-dimensional plan for the integrated circuit provided with relative positions of a multiple number of functional units, a step for superposing a power grid over the two-dimensional plan, a step for dividing the two dimensional plan and the power grid into a multiple number of ranges and for determining support decoupling capacitance value necessary for supporting the voltage of the power grid for each region, a step for determining a specific capacitance value, a step to determine a necessary decoupling capacitance value, based on the support decoupling capacitance value and the specific capacitance value, a step for determining a decoupling condenser region for the necessary decoupling condenser capacitance value and a step for correcting a circuit area within the region, based on the decoupling condenser region are contained.

公开(公告)号：JP2002083873A

公开(公告)日：2002-03-22

申请号：JP2001209910

申请日：2001-07-10

Applicant: IBM

Inventor： ALLEN ARCHIBALD J ,  BULA OREST ,  COHN JOHN M ,  COLE DANIEL ,  CONRAD EDWARD W ,  LEIPOLD WILLIAM C

IPC: H01L21/822 ,  H01L21/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor chip structure and a method for integrating a decoupling capacitor and an OPC structure. SOLUTION: The semiconductor chip structure is provided with a first area having a first cell for storing and processing data, and a second region outside the first region having the OPC structure provided with the decoupling capacitor. The line width of the active gate of the first cell is the same size as or size almost similar to the OPC structure. The OPC structure reduces the proximity effect of an active device in the first cell and is provided with N-type and P-type FET located in the second region. The OPC structure has a width greater than the first cell as well. The second region is composed of multiple OPC structure so that the second region is provided with multiple decoupling capacitors. The active device in the first cell is separated by a first distance, and the OPC structure is separated from the active device by the first distance.

公开(公告)号：WO2005008732A3

公开(公告)日：2007-07-05

申请号：PCT/US2004022267

申请日：2004-07-09

Applicant: IBM ,  BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

IPC: G11C16/04 ,  G11C19/08 ,  H01L20060101

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

Abstract: A structure for processing data on a semiconductor device comprising an input island (14), a processing island (8), and an output island (12) formed on the semiconductor device (18). The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

Abstract translation: 一种用于在半导体器件上处理数据的结构，包括形成在半导体器件（18）上的输入岛（14），处理岛（8）和输出岛（12）。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

公开(公告)号：AU2002357881A1

公开(公告)日：2004-07-29

申请号：AU2002357881

申请日：2002-12-17

Applicant: IBM

Inventor： MCCULLEN JUDITH H ,  PRUE SARAH ,  SITKO MICHAEL H ,  BOUCHER MATT ,  COHN JOHN M ,  DAUPHIN RICHARD ,  MASTERS MARK

IPC: G06F9/45 ,  G06F17/50 ,  G06K9/00 ,  G06T7/00

Abstract: The invention provides a method, system (12), and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit (S2). Based on the image(s), a component netlist is generated (S3, S305, S315). Further, a logic netlist is generated (S4) by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic (50) based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

公开(公告)号：DE602004020620D1

公开(公告)日：2009-05-28

申请号：DE602004020620

申请日：2004-07-09

Applicant: IBM

Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

IPC: H01L21/00 ,  G06F1/32 ,  G11C5/14 ,  G11C19/08 ,  H01L20060101

Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

公开(公告)号：AT429015T

公开(公告)日：2009-05-15

申请号：AT04778016

申请日：2004-07-09

Applicant: IBM

Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH ,  STOUT DOUGLAS ,  VENTRONE SEBASTIAN

IPC: G11C16/04 ,  G06F1/32 ,  G11C5/14 ,  G11C19/08 ,  H01L20060101

Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.