公开(公告)号：DE102006001117B9

公开(公告)日：2009-04-16

申请号：DE102006001117

申请日：2006-01-09

Applicant: IBM ,  QIMONDA AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/06 ,  G11C7/12 ,  H03F3/195

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

公开(公告)号：DE602004008465T2

公开(公告)日：2008-05-21

申请号：DE602004008465

申请日：2004-06-08

Applicant: QIMONDA AG ,  IBM

Inventor： DEBROSSE JOHN ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/16 ,  G11C11/15

公开(公告)号：DE602004009308D1

公开(公告)日：2007-11-15

申请号：DE602004009308

申请日：2004-05-26

Applicant: IBM ,  QIMONDA AG

Inventor： DEBROSSE JOHN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/12 ,  G11C8/08 ,  G11C11/16 ,  G11C11/40

公开(公告)号：DE102004014244A1

公开(公告)日：2004-11-25

申请号：DE102004014244

申请日：2004-03-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BUKOFSKY SCOTT ,  DEBROSSE JOHN ,  HUG MARCO ,  LIEBMANN LARS W ,  NICKEL DANIEL JOHN ,  PREUNINGER JUERGEN

IPC: G03F1/30 ,  G03F7/20 ,  G03F9/00 ,  G03F1/00

Abstract: A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.

公开(公告)号：AT503252T

公开(公告)日：2011-04-15

申请号：AT07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL ,  CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  DEBROSSE JOHN ,  HSU LOUIS ,  RADENS CARL ,  WONG KEITH ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

公开(公告)号：DE69841838D1

公开(公告)日：2010-09-30

申请号：DE69841838

申请日：1998-06-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  DEBROSSE JOHN

IPC: H01L21/8242 ,  H01L27/108 ,  G11C11/4097

公开(公告)号：DE60305208D1

公开(公告)日：2006-06-14

申请号：DE60305208

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：AU2003294886A8

公开(公告)日：2004-07-14

申请号：AU2003294886

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR WILLIAM ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：SG53118A1

公开(公告)日：1998-09-28

申请号：SG1997003935

申请日：1997-11-01

Applicant: IBM

Inventor： DEBROSSE JOHN ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C29/00 ,  G11C11/401 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

Abstract: Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator.

公开(公告)号：DE102006001117B4

公开(公告)日：2008-11-27

申请号：DE102006001117

申请日：2006-01-09

Applicant: IBM ,  QIMONDA AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/06 ,  G11C7/12 ,  H03F3/195

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.