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    DRAM STRUCTURE HAVING DEEP TRENCH BASE AND MANUFACTURING METHOD THEREFOR
    11.
    发明专利
    DRAM STRUCTURE HAVING DEEP TRENCH BASE AND MANUFACTURING METHOD THEREFOR 失效

    公开(公告)号：JP2000012801A

    公开(公告)日：2000-01-14

    申请号：JP14714699

    申请日：1999-05-26

    Applicant: IBM ,  SIEMENS AG

    Inventor： ECONOMIKOS LAERTIS ,  GRUENING ULRIKE ,  HO HERBERT L ,  RADENS CARL J ,  JAMMY RAGARAO ,  HOEPFNER JOACHIM ,  SHEN HUA

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

    Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned collar and a buried plate while forming a reliable node dielectrics on the collar without requiring a plurality of independent trench recesses for forming the buried plate and the collar. SOLUTION: Etching for a trench is made within a surface of a semiconductor substrate 10 and a dielectric material layer is formed on a side wall 12 of the trench. The dielectric material layer is partially eliminated to expose a lower base region of the upper part of the trench side wall 12. After that an oxide layer is made to grow on the upper part of the side wall 12. The dielectric layer is eliminated from a remaining part of the side wall 12 and a buried plate 17 is formed by doping. The dielectric layer includes the upper part of the collar and a node, (i,e, the trench wall at a portion of the buried plate 17) and is provided for the trench wall. An inner electrode 19 is formed at the inner part of the trench.

    LOW TEMPERATURE DIFFUSION METHOD FOR RAISING DOPANT CONCENTRATION
    14.
    发明专利
    LOW TEMPERATURE DIFFUSION METHOD FOR RAISING DOPANT CONCENTRATION 失效

    公开(公告)号：JPH11251258A

    公开(公告)日：1999-09-17

    申请号：JP33884498

    申请日：1998-11-30

    Applicant: IBM ,  SIEMENS AG

    Inventor： ECONOMIKOS LAERTIS ,  MURTHY CHERUVU S ,  SHEN HUA

    IPC: H01L21/225 ,  H01L21/334 ,  H01L21/822 ,  H01L23/00 ,  H01L27/04 ,  H01L29/94

    Abstract: PROBLEM TO BE SOLVED: To do so as to obtain a high dopant concn. in a small semiconductor region without excessively expanding a doping region by capping a dopant- containing oxide glass layer deposited on a semiconductor surface with a conformal silicon oxide layer, and heating the obtained substrate in an oxidative atmosphere. SOLUTION: A dopant-containing oxide glass layer 60 is deposited on a substrate surface to be doped, the dopant-containing oxide glass layer 60 is formed on a trench wall surface 61 of the substrate by the low pressure chemical vapor deposition method, and the dopant-containing oxide glass is pref. a silicate glass. By a conformal oxide layer 62 deposited to cover the dopant- containing oxide glass layer 60, it is capped. The conformal oxide is preferably a silicon oxide formed by the plasma-intensified CVD using, e.g. SiH4 /O2 below 500 deg.C. The dopant-containing oxide glass is heat treated in a nonoxidative atmosphere and then in an oxidative atmosphere.

    APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SIMULATION OF MANUFACTURING EFFECTS DURING INTEGRATED CIRCUIT DESIGN
    16.
    发明专利
    APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SIMULATION OF MANUFACTURING EFFECTS DURING INTEGRATED CIRCUIT DESIGN 未知

    公开(公告)号：SG160271A1

    公开(公告)日：2010-04-29

    申请号：SG2009048448

    申请日：2009-07-17

    Applicant: IBM

    Inventor： XIANG HUA ,  ECONOMIKOS LAERTIS ,  FAYAZ MOHAMMED FAZIL ,  PURI RUCHIR ,  GRECO STEPHEN EDWARD ,  O NEIL PATRICIA A

    Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

    17.
    发明专利
    未知

    公开(公告)号：DE60329621D1

    公开(公告)日：2009-11-19

    申请号：DE60329621

    申请日：2003-11-14

    Applicant: IBM

    Inventor： ECONOMIKOS LAERTIS ,  DELIGIANNI HARIKLIA ,  COTTE JOHN M ,  GRABARZ HENRY J ,  CHEN BOMY

    IPC: C25D5/22 ,  C25D5/48 ,  C25D7/12 ,  C25D17/00 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768

    Abstract: A method and apparatus are described for performing both electroplating of a metal layer and planarization of the layer on a substrate. Electroplating and electroetching of metal (such as copper) are performed in a repeated sequence, followed by chemical-mechanical polishing. An electroplating solution, electroetching solution, and a non-abrasive slurry are dispensed on a polishing pad in the respective process steps. The substrate is held against the pad with a variable force in accordance with the process, so that the spacing between substrate and pad may be less during electroplating than during electroetching.

    18.
    发明专利
    未知

    公开(公告)号：DE10226235A1

    公开(公告)日：2003-01-16

    申请号：DE10226235

    申请日：2002-06-13

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： ECONOMIKOS LAERTIS ,  SIMPSON ALEXANDER

    IPC: B24B57/02 ,  B24B37/04 ,  C09K3/14 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/76

    Abstract: The invention provides fixed-abrasive chemical-mechanical polishing processes which are effective in rapidly reducing thickness of oxide layers, especially siliceous oxides. The processes of the invention are preferably characterized by at least one step involving simultaneous use of a fixed-abrasive polishing element and an aqueous liquid medium containing an abrasive. Where the original oxide layer has topographic variation, the thickness reduction technique of the invention may be preceeded by topography reduction step using a fixed-abrasive and an aqueous medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide layer on the substrate.

    19.
    发明专利
    未知

    公开(公告)号：DE10354717A1

    公开(公告)日：2004-07-15

    申请号：DE10354717

    申请日：2003-11-22

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： BEINTNER JOCHEN ,  ECONOMIKOS LAERTIS ,  KNORR ANDREAS ,  WISE MICHAEL L

    IPC: H01L21/304 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242

    Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

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