公开(公告)号：SG147368A1

公开(公告)日：2008-11-28

申请号：SG2008021305

申请日：2008-03-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： WUPING LIU ,  FITZSIMMONS JOHN A ,  BECK MICHAEL

Abstract: INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical- mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

公开(公告)号：MY134796A

公开(公告)日：2007-12-31

申请号：MYPI20030029

申请日：2003-01-06

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: AN ADVANCED BACK-END-OF-LINE (BEOL) METALLIZATION STRUCTURE IS DISCLOSED. THE STRUCTURE INCLUDES A BILAYER DIFFUSION BARRIER OR CAP, WHERE THE FIRST CAP LAYER (116, 123) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP CVD) PROCESS, AND THE SECOND CAP LAYER (117, 124) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PE CVD) PROCESS. A METHOD FOR FORMING THE BEOL METALLIZATION STRUCTURE IS ALSO DISCLOSED. THE INVENTION IS PARTICULARLY USEFUL IN INTERCONNECT STRUCTURES COMPRISING LOW-K DIELECTRIC MATERIAL FOR THE INTER-LAYER DIELECTRIC (ILD) AND COPPER FOR THE CONDUCTORS.

公开(公告)号：AU2002360420A1

公开(公告)日：2003-07-30

申请号：AU2002360420

申请日：2002-11-22

Applicant: IBM

Inventor： WANG YUN YU ,  GATES STEPHEN ,  AGARWALA BIRENDRA N ,  FITZSIMMONS JOHN A ,  LEE JIA ,  LUSTIG NAFTALI E

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L21/469 ,  H01L21/4763

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k). The cap layer is formed of amorphous nitrogenated hydrogenated silicon cabride, and has a dielectric constant (k) of less than about 5. A method for forming the BEOL metallization structure is also disclosed, where the cap layer is deposited using a plasma-enhanced chemical vapor deposition (PE CVD) process. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.