公开(公告)号：AU2002346512A1

公开(公告)日：2003-07-30

申请号：AU2002346512

申请日：2002-11-22

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

公开(公告)号：SG147368A1

公开(公告)日：2008-11-28

申请号：SG2008021305

申请日：2008-03-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： WUPING LIU ,  FITZSIMMONS JOHN A ,  BECK MICHAEL

Abstract: INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical- mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

公开(公告)号：MY134796A

公开(公告)日：2007-12-31

申请号：MYPI20030029

申请日：2003-01-06

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: AN ADVANCED BACK-END-OF-LINE (BEOL) METALLIZATION STRUCTURE IS DISCLOSED. THE STRUCTURE INCLUDES A BILAYER DIFFUSION BARRIER OR CAP, WHERE THE FIRST CAP LAYER (116, 123) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP CVD) PROCESS, AND THE SECOND CAP LAYER (117, 124) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PE CVD) PROCESS. A METHOD FOR FORMING THE BEOL METALLIZATION STRUCTURE IS ALSO DISCLOSED. THE INVENTION IS PARTICULARLY USEFUL IN INTERCONNECT STRUCTURES COMPRISING LOW-K DIELECTRIC MATERIAL FOR THE INTER-LAYER DIELECTRIC (ILD) AND COPPER FOR THE CONDUCTORS.

公开(公告)号：EP1470580A4

公开(公告)日：2005-07-20

申请号：EP02784578

申请日：2002-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer (116, 123) is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer (117, 124) is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract translation: 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由优选沉积的介电材料形成 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：EP2047506A4

公开(公告)日：2012-04-25

申请号：EP07783916

申请日：2007-05-18

Applicant: IBM

Inventor： STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2008016740A3

公开(公告)日：2008-06-26

申请号：PCT/US2007069219

申请日：2007-05-18

Applicant: IBM ,  STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

Inventor： STANDAERT THEODORUS E ,  DAVIS PEGEEN M ,  FITZSIMMONS JOHN A ,  GRECO STEPHEN E ,  KO TZE-MAN ,  LUSTIG NAFTALI E ,  NICHOLSON LEE M ,  SANKARAN SUJATHA

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract translation: 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在所述ILD材料中形成一个或多个通孔开口; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬里; 在由所述第一衬里覆盖的所述一个或多个通孔开口中的至少一个的顶部上创建一个或多个沟槽开口; 以及形成覆盖沟槽开口和第一衬里的至少一部分的第二衬里。 还提供了由该方法形成的互连结构。

公开(公告)号：AU2003217368A1

公开(公告)日：2003-09-09

申请号：AU2003217368

申请日：2003-02-06

Applicant: IBM

Inventor： FITZSIMMONS JOHN A ,  GATES STEPHEN M ,  MCGAHAY VINCENT J

IPC: H01L23/26 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit structure comprises a main dielectric layer having a top surface. A cavity having sidewalls is formed in the main dielectric layer. A liner is formed on the sidewalls of the cavity. A metal conductor such as copper is formed over the liner filling the lined cavity. A getter layer is formed in the structure which combines with oxygen/moisture to form inert reaction products thereof. The getter layer can be either a conductive material which can be included in the liner or a dielectric layer which can be formed on top of the main dielectric layer, buried in the main dielectric layer or below the main dielectric layer.

公开(公告)号：AU2003217368A8

公开(公告)日：2003-09-09

申请号：AU2003217368

申请日：2003-02-06

Applicant: IBM

Inventor： GATES STEPHEN M ,  MCGAHAY VINCENT J ,  FITZSIMMONS JOHN A

IPC: H01L23/26 ,  H01L23/522 ,  H01L23/532 ,  H01L29/41

Abstract: An integrated circuit structure comprises a main dielectric layer having a top surface. A cavity having sidewalls is formed in the main dielectric layer. A liner is formed on the sidewalls of the cavity. A metal conductor such as copper is formed over the liner filling the lined cavity. A getter layer is formed in the structure which combines with oxygen/moisture to form inert reaction products thereof. The getter layer can be either a conductive material which can be included in the liner or a dielectric layer which can be formed on top of the main dielectric layer, buried in the main dielectric layer or below the main dielectric layer.

公开(公告)号：DE112014000384T5

公开(公告)日：2015-09-24

申请号：DE112014000384

申请日：2014-01-07

Applicant: IBM

Inventor： FITZSIMMONS JOHN A ,  CHENG TIEN-JEN ,  FAROOQ MUKTA G

IPC: H01L23/48

Abstract: Die vorliegende Erfindung stellt eine stabilisierte fein texturierte Metallmikrostruktur bereit, die eine dauerfeste aktivierte Fläche 310 bildet, die zum Bonden eines 3D-Stacked Chips verwendbar ist. Eine feinkörnige Schicht, die der Selbstheilung widersteht, ermöglicht ein Bonden von Metall auf Metall in moderater Zeit und Temperatur und mit einer höheren Prozessflexibilität.