公开(公告)号：AU2002346512A1

公开(公告)日：2003-07-30

申请号：AU2002346512

申请日：2002-11-22

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

公开(公告)号：MY134796A

公开(公告)日：2007-12-31

申请号：MYPI20030029

申请日：2003-01-06

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: AN ADVANCED BACK-END-OF-LINE (BEOL) METALLIZATION STRUCTURE IS DISCLOSED. THE STRUCTURE INCLUDES A BILAYER DIFFUSION BARRIER OR CAP, WHERE THE FIRST CAP LAYER (116, 123) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP CVD) PROCESS, AND THE SECOND CAP LAYER (117, 124) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PE CVD) PROCESS. A METHOD FOR FORMING THE BEOL METALLIZATION STRUCTURE IS ALSO DISCLOSED. THE INVENTION IS PARTICULARLY USEFUL IN INTERCONNECT STRUCTURES COMPRISING LOW-K DIELECTRIC MATERIAL FOR THE INTER-LAYER DIELECTRIC (ILD) AND COPPER FOR THE CONDUCTORS.

公开(公告)号：EP1470580A4

公开(公告)日：2005-07-20

申请号：EP02784578

申请日：2002-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer (116, 123) is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer (117, 124) is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract translation: 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由优选沉积的介电材料形成 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：EP1839338A4

公开(公告)日：2011-11-09

申请号：EP05854112

申请日：2005-12-14

Applicant: IBM

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

IPC: H01L29/04 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

公开(公告)号：EP1979932A4

公开(公告)日：2012-03-14

申请号：EP07710130

申请日：2007-01-15

Applicant: IBM

Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

IPC: H01L21/77 ,  H01L21/302 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1974379A4

公开(公告)日：2011-06-01

申请号：EP07710226

申请日：2007-01-19

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DOWNES KEITH E ,  LINDGREN PETER J ,  STAMPER ANTHONY K

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2313921A4

公开(公告)日：2014-08-27

申请号：EP09805365

申请日：2009-07-28

Applicant: IBM

Inventor： COLLINS DAVID S ,  JOSEPH ALVIN ,  LINDGREN PETER J ,  STAMPER ANTHONY K ,  WATSON KIMBALL M

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

公开(公告)号：EP2250669A4

公开(公告)日：2012-07-25

申请号：EP09710899

申请日：2009-02-11

Applicant: IBM

Inventor： LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  STEIN KENNETH J

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和由环形导体层包围的塞子层。 一种用于制造穿通基底通孔的方法，包括在基底内形成盲孔，并且在盲孔内依次形成并随后在盲孔内进行平坦化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：JP2005203779A

公开(公告)日：2005-07-28

申请号：JP2005003396

申请日：2005-01-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAMBINO JEFFREY P ,  STAMPER ANTHONY K

IPC: H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a low-resistive interconnect structure on and in a rigid low-k interlayer dielectric layer.
SOLUTION: The method comprises the steps of providing a lower metal wiring layer having first metal lines 26 positioned within a lower low-k dielectric 32, depositing an upper low-k dielectric 6 on the lower metal wiring layer, etching at least one portion of the upper low-k dielectric to provide at least one via 24 to the first metal lines, forming rigid dielectric sidewall spacers 12 in at least one via of the upper low-k dielectric, and forming second metal lines 25 in at least one portion of the upper low-k dielectric.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在刚性低k层间电介质层上和其中形成低电阻互连结构的方法。 解决方案：该方法包括以下步骤：提供具有位于下部低k电介质32内的第一金属线26的下金属布线层，在下金属布线层上沉积上部低k电介质6，至少蚀刻 上部低k电介质的一部分，以将至少一个通孔24提供给第一金属线，在上部低k电介质的至少一个通孔中形成刚性电介质侧壁间隔件12，并至少形成第二金属线25 上部低k电介质的一部分。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：EP2011208A4

公开(公告)日：2011-09-28

申请号：EP07759794

申请日：2007-03-30

Applicant: IBM

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207