公开(公告)号：AU2002346512A1

公开(公告)日：2003-07-30

申请号：AU2002346512

申请日：2002-11-22

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

公开(公告)号：MY134796A

公开(公告)日：2007-12-31

申请号：MYPI20030029

申请日：2003-01-06

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: AN ADVANCED BACK-END-OF-LINE (BEOL) METALLIZATION STRUCTURE IS DISCLOSED. THE STRUCTURE INCLUDES A BILAYER DIFFUSION BARRIER OR CAP, WHERE THE FIRST CAP LAYER (116, 123) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP CVD) PROCESS, AND THE SECOND CAP LAYER (117, 124) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PE CVD) PROCESS. A METHOD FOR FORMING THE BEOL METALLIZATION STRUCTURE IS ALSO DISCLOSED. THE INVENTION IS PARTICULARLY USEFUL IN INTERCONNECT STRUCTURES COMPRISING LOW-K DIELECTRIC MATERIAL FOR THE INTER-LAYER DIELECTRIC (ILD) AND COPPER FOR THE CONDUCTORS.

公开(公告)号：EP1470580A4

公开(公告)日：2005-07-20

申请号：EP02784578

申请日：2002-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer (116, 123) is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer (117, 124) is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract translation: 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由优选沉积的介电材料形成 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：JP2003229464A

公开(公告)日：2003-08-15

申请号：JP2002330937

申请日：2002-11-14

Applicant: IBM

Inventor： KANE TERENCE L ,  WANG YUN YU ,  CAMBRA MALCOLM P JR ,  TENNEY MICHAEL P

IPC: H01L21/66 ,  H01L23/544 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device monitor structure which can detect localized defects due to floating-body effects, particularly on SOI device wafers. SOLUTION: The semiconductor device monitor structure includes a plurality of cells containing PFET or NFET device, disposed at a perimeter of the semiconductor device monitor structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structure having a specific spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and the second distance are non-uniform between the cells. The cells may be turned to bit file map for single-cell failures, thereby enabling detection of the localized defects due to the floating-body effects. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2007243187A

公开(公告)日：2007-09-20

申请号：JP2007052225

申请日：2007-03-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEITH KWONG HON WONG ,  WILDMAN HORATIO S ,  YANG CHIH-CHAO ,  WANG YUN YU ,  CHRISTOPHER C PARKS

IPC: H01L21/28 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L23/485 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide new MOL metallurgy for avoiding a defect by using the MOL metallurgy of a prior art and its manufacturing method. SOLUTION: There is provided a semiconductor structure comprising a Co-containing liner arranged between an oxygen getter layer and a conductive material containing metal. The Co-containing liner, the oxygen getter layer, and the conductive material containing the metal form MOL metallurgy in which the Co-containing liner substitutes a conventional TiN liner. "Co-containing" means containing elemental Co only or containing at least one of elemental Co and P or B. The Co-containing liner is formed by an electroless deposition process in order to provide the Co-containing liner of fine step coatability using the inside of the contact opening of a high aspect ratio. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过使用现有技术的MOL冶金及其制造方法来提供新的MOL冶金以避免缺陷。 解决方案：提供一种半导体结构，其包括布置在氧气吸气剂层和含有金属的导电材料之间的含Co衬里。 含Co的内衬，吸氧剂层和含有MOL冶金金属的导电材料，其中Co含量的衬垫取代了常规的TiN衬里。 “含Co”是指仅含有元素Co或含有元素Co和P或B中的至少一种。通过无电沉积方法形成含Co的内衬，以便使用 在高宽比的接触开口的内部。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005311366A

公开(公告)日：2005-11-04

申请号：JP2005119003

申请日：2005-04-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  CHIRAS STEFANIE R ,  DALTON TIMOTHY ,  DEMAREST JAMES J ,  DUNN DERREN N ,  DZIOBKOWSKI CHESTER T ,  FLAITZ PHILIP L ,  LANE MICHAEL W ,  LLOYD JAMES R ,  DARYL D RESUTAINO ,  SHAW THOMAS M ,  WANG YUN YU ,  YANG CHIH-CHAO

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To realize an interconnection structure that improves the adhesion between an upper low-k dielectric layer and a diffusion barrier cap dielectric layer existing therebeneath. SOLUTION: In the interconnection structure, adhesion between the upper low-k (for example, the dielectric coefficient is less than 4.0) dielectric layer (for example, a dielectric containing an element group consisting of Si, C, O, and H) and the diffusion barrier cap dielectric layer (for example, a cap layer containing an element group consisting of C, Si, N, and H) existing therebeneath is improved, by providing an adhesion transition layer in between the two layers. Because the adhesion transition layer exists between the upper low-k dielectric layer and the diffusion barrier cap dielectric layer, the possibility that the layers in the interconnection structure are separated in a packaging process is reduced. The adhesion transition layer provided here comprises a lower SiO x (or SiON) contained region and an upper C inclination region. Such a structure and, in particular, a method for forming an adhesion transition layer are also provided. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：实现改善上部低k电介质层和存在于其之间的扩散阻挡盖电介质层之间的粘附性的互连结构。 解决方案：在互连结构中，上部低k（例如，介电系数小于4.0）电介质层（例如，包含由Si，C，O和 H）和扩散阻挡盖电介质层（例如，包含由C，Si，N和H构成的元素组的覆盖层）提高，通过在两层之间提供粘合过渡层。 由于粘附过渡层存在于上部低k电介质层和扩散阻挡层电介质层之间，因此在封装过程中互连结构中的层分离的可能性降低。 这里提供的粘合过渡层包含较低的SiO xS（或SiON）含有区域和上C倾斜区域。 还提供了这种结构，特别是形成粘附过渡层的方法。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2002334850A

公开(公告)日：2002-11-22

申请号：JP2002096570

申请日：2002-03-29

Applicant: IBM

Inventor： GIEWONT KENNETH J ,  WANG YUN YU ,  RUSSELL AANTO ,  RANSOM CRAIG ,  COFFIN JUDITH ,  DOMENICUCCI ANTHONY ,  MACDONALD MICHAEL ,  JOHNSON BRIAN E

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/336 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a high-quality silicide layer having a high sheet resistance. SOLUTION: A method of preparing a semiconductor material for forming the silicide layer in selected areas is disclosed. In the representative embodiment, the method includes a step of removing at least one of a nitride film and an oxynitride film from the selected area, a step of removing metallic particles from the selected area, and a step of removing surface particles from the selected area. The method also includes a step of removing organics from the selected areas and a step of removing an oxide film layer from the selected areas.

公开(公告)号：DE10393309T5

公开(公告)日：2005-12-29

申请号：DE10393309

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CABRAL CYRIL JR ,  IGGULDEN ROY C ,  MCSTAY IRENE LENNOX ,  CLEVENGER LAWRENCE A ,  WANG YUN YU ,  WONG KEITH KWONG HON ,  ROBL WERNER ,  GLUSCHENKOV OLEG ,  MALIK RAJEEV ,  SCHUTZ RONALD J

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：DE10331195A1

公开(公告)日：2004-02-12

申请号：DE10331195

申请日：2003-07-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID M ,  FALTERMEIER JOHNATHAN ,  FLAITZ PHILIP ,  IWATAKE MICHAEL M ,  MALDEI MICHAEL ,  NINOMIYA LISA Y ,  RAMACHARDRAN RAVIKUMAR ,  SARDESAI VIRAI Y ,  SNAVELY COLLEEN M ,  WANG YUN YU

IPC: H01L21/20 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8242

Abstract: In a method of preparing a DRAM wherein doped poly-Si is used as a CB contact as well as a source of doping in the contact region, and where in amorphous Si is used to fill the CB contact, the improvement of enhancing epitaxial regrowth in amorphous Poly CB contacts, comprising: a) affecting a CB liner reactive ion etch on a substrate to remove SiN and SiO; b) affecting an O plasma clean (in-situ or ex-situ); c) affecting a Huang AB clean; d) affecting a dilute hydrofluoric acid (DHF) clean; e) depositing amorphous Si; and f) annealing to recrystallize and regrow amorphous CB.

公开(公告)号：DE10331195B4

公开(公告)日：2006-12-28

申请号：DE10331195

申请日：2003-07-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID M ,  FALTERMEIER JOHNATHAN ,  FLAITZ PHILIP ,  IWATAKE MICHAEL M ,  MALDEI MICHAEL ,  NINOMIYA LISA Y ,  RAMACHARDRAN RAVIKUMAR ,  SARDESAI VIRAI Y ,  SNAVELY COLLEEN M ,  WANG YUN YU

IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/285 ,  H01L21/306

Abstract: In a method of preparing a DRAM wherein doped poly-Si is used as a CB contact as well as a source of doping in the contact region, and where in amorphous Si is used to fill the CB contact, the improvement of enhancing epitaxial regrowth in amorphous Poly CB contacts, comprising: a) affecting a CB liner reactive ion etch on a substrate to remove SiN and SiO; b) affecting an O plasma clean (in-situ or ex-situ); c) affecting a Huang AB clean; d) affecting a dilute hydrofluoric acid (DHF) clean; e) depositing amorphous Si; and f) annealing to recrystallize and regrow amorphous CB.