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    A DUAL DAMASCENE INTEGRATION SCHEME USING A BILAYER INTERLEVEL DIELECTRIC
    3.
    发明申请
    A DUAL DAMASCENE INTEGRATION SCHEME USING A BILAYER INTERLEVEL DIELECTRIC 审中-公开
    使用双层交互式电介质的双重DAMASCENE集成方案

    公开(公告)号：WO02054483A3

    公开(公告)日：2003-06-05

    申请号：PCT/US0147376

    申请日：2001-12-04

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： KALTALIOGLU ERDEM

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76808 ,  H01L2221/1031 ,  H01L2221/1036

    Abstract: A semiconductor structure includes a semiconductor substrate and a dielectric layer disposed over the substrate, the dielectric layer having a first trench. A first metal layer is disposed in the first trench. A first layer of a material having a first dielectric constant is disposed over the dielectric layer, the first layer having a via in registration with the metal disposed in the first trench. A second layer of a material having a second dielectric constant is disposed over the first layer of material, the second layer having a second trench in registration with the via. The first dielectric constant is higher than the second dielectric constant. A second metal layer is disposed in the via and second trench, the second metal layer being in contact with the first metal layer.

    Abstract translation: 半导体结构包括半导体衬底和设置在衬底上的电介质层，电介质层具有第一沟槽。 第一金属层设置在第一沟槽中。 具有第一介电常数的材料的第一层设置在电介质层上，第一层具有通孔，该通孔与布置在第一沟槽中的金属对准。 具有第二介电常数的材料的第二层设置在第一材料层之上，第二层具有与通孔对准的第二沟槽。 第一介电常数高于第二介电常数。 第二金属层设置在通孔和第二沟槽中，第二金属层与第一金属层接触。

    BARBED VIAS FOR ELECTRICAL AND MECHANICAL CONNECTION BETWEEN CONDUCTIVE LAYERS IN SEMICONDUCTOR DEVICES
    4.
    发明申请
    BARBED VIAS FOR ELECTRICAL AND MECHANICAL CONNECTION BETWEEN CONDUCTIVE LAYERS IN SEMICONDUCTOR DEVICES 审中-公开
    用于半导体器件中的导电层之间的电气和机械连接的平衡VIAS

    公开(公告)号：WO02054446A3

    公开(公告)日：2003-11-06

    申请号：PCT/US0147380

    申请日：2001-12-04

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： BARTH HANS-JOACHIM ,  KALTALIOGLU ERDEM

    IPC: H01L20060101 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76852 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A multi-layer integrated circuit (400) and method of manufacturing thereof having barbed vias (427) connecting conductive lines (468, 408). Circuit (400) includes a first dielectric layer (404) deposited on a substrate (402) and conductive lines (408) formed in the first dielectric layer (404). A second dielectric layer (462) is deposited over the first dielectric layer (404). Barbed vias (427) are formed having a substantially cylindrical portion (424) within the second dielectric layer (462) and a barbed portion (426) within conductive lines (408). Conductive lines (468) are formed over the barbed vias (427) within a the second dielectric layer (462). A region of the barbed via (427) barbed portion (406) extends beneath the second dielectric layer (462).

    Abstract translation: 一种多层集成电路（400）及其制造方法，其具有连接导线（468,408）的带倒钩的过孔（427）。 电路（400）包括沉积在衬底（402）上的第一介电层（404）和形成在第一介电层（404）中的导电线路（408）。 在第一介电层（404）上沉积第二介电层（462）。 带刺通孔（427）形成为在第二电介质层（462）内具有基本上圆柱形的部分（424）和在导线（408）内的有倒钩的部分（426）。 导电线（468）形成在第二电介质层（462）内的带倒钩的过孔（427）上。 倒钩通孔（427）倒钩部分（406）的区域在第二介电层（462）的下方延伸。

    DUAL DAMASCENE PROCESS UTILIZING A LOW-K DUAL DIELECTRIC
    5.
    发明申请
    DUAL DAMASCENE PROCESS UTILIZING A LOW-K DUAL DIELECTRIC 审中-公开
    使用低K双电介质的双金刚石工艺

    公开(公告)号：WO0199184A3

    公开(公告)日：2002-06-27

    申请号：PCT/US0119881

    申请日：2001-06-21

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： STETTER MICHAEL ,  KALTALIOGLU ERDEM ,  COWLEY ANDY

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of fabricating an integrated circuit with a dual dielectric structure and utilizes a dual damascene process to fabricate metal interconnection layers. The dual dielectric structure consists of a first insulating layer (24) of conventional dielectric material, and a second insulating layer (26) of a second dielectric material with a low dielectric constant (low-k dielectric material). The first dielectric material is used in regions of the integrated circuit where the superior mechanical properties of conventional dielectric materials will result in maintaining the reliability and mechanical properties of the integrated circuit. The second dielectric material is used in regions of the integrated circuit where the low dielectric constant will result in improved speed of the integrated circuit and reduced electrical coupling between conductors in the integrated circuit. The fabrication of the dual dielectric structure is integrated with a dual damascene metallization process.

    Abstract translation: 一种制造具有双电介质结构的集成电路的方法，并利用双镶嵌工艺来制造金属互连层。 双电介质结构由常规介电材料的第一绝缘层（24）和具有低介电常数（低k电介质材料）的第二介电材料的第二绝缘层（26）组成。 第一介电材料用于集成电路的区域，其中传统介电材料的优良机械性能将导致保持集成电路的可靠性和机械性能。 第二介电材料用于集成电路的区域，其中低介电常数将导致集成电路的改进的速度和减小集成电路中的导体之间的电耦合。 双电介质结构的制造与双镶嵌金属化工艺集成。

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