公开(公告)号：JP2004088101A

公开(公告)日：2004-03-18

申请号：JP2003287197

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  FRIED DAVID M ,  GAUTHIER JR ROBERT J ,  EDWARD J NOWAKU ,  RANKIN JED H ,  TONTI WILLIAM R

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

Abstract: PROBLEM TO BE SOLVED: To provide an improved manufacturing method of an integrated circuit which is made by incorporating both a FinFET and a thick-body device into a single chip. SOLUTION: This manufacturing method of a microelectronic circuit which is made by incorporating both a fin-type field-effect transistor (FinFET) 1801 and a thick-body device 1802 into a single chip can attain an efficiency higher than that of the conventional methods by utilizing common masks and processes. Reduction in the numbers of masks and processes is achieved by utilizing common masks and processes together with several reduction strategies. For example, a structure which usually accompanies a FinFET is formed on a side surface of a thick silicon mesa. A bulk of the silicon mesa is doped to connect to a body contact formed on the opposite side surface of the mesa. This invention also includes the FinFET, thick-body device, and a chip manufactured by the methods associated with the invention. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003204068A

公开(公告)日：2003-07-18

申请号：JP2002361664

申请日：2002-12-13

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetrical field effect transistor (FET) having a threshold voltage which is compatible with the present CMOS circuit design and a low-resistance gate electrode. SOLUTION: This asymmetrical FET contains a structure integrated with a p-type gate portion and an n-type gate portion provided on the main body of a vertical semiconductor and the interconnection between the gate portions and a flattened structure on the interconnection. Because of the integrated Fin FET/thick polycilicon-containing gate structure, an Fin FET having the threshold voltage which is compatible with the present CMOS circuit design and the gate electrode the resistivity of which is lower than that of the conventional symmetrical Fin FET can be manufactured. The asymmetrical FET contains the n-type gate portion and p-type gate portion on the main body of the vertical semiconductor and the interconnection between the gate portions and the flattened structure on the interconnection. COPYRIGHT: (C)2003,JPO

公开(公告)号：DE60236375D1

公开(公告)日：2010-06-24

申请号：DE60236375

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J ,  FRIED DAVID M

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

公开(公告)号：AU2002368525A1

公开(公告)日：2004-07-22

申请号：AU2002368525

申请日：2002-12-20

Applicant: IBM

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M ,  RANKIN JED H

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12 ,  H01L21/44

公开(公告)号：AU2003237320A8

公开(公告)日：2003-12-19

申请号：AU2003237320

申请日：2003-06-03

Applicant: IBM

Inventor： SADANA DEVENDRA K ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  FRIED DAVID M

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8232

Abstract: The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：AU2003237320A1

公开(公告)日：2003-12-19

申请号：AU2003237320

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786

Abstract: The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：AU2003223306A1

公开(公告)日：2003-10-08

申请号：AU2003223306

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

公开(公告)号：AU2002364088A1

公开(公告)日：2004-07-22

申请号：AU2002364088

申请日：2002-12-19

Applicant: IBM

Inventor： RAINEY BETHANN ,  FRIED DAVID M ,  NOWAK EDWARD J

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786

公开(公告)号：DE10296953T5

公开(公告)日：2004-04-29

申请号：DE10296953

申请日：2002-06-06

Applicant: IBM

Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

公开(公告)号：AU2003223306A8

公开(公告)日：2003-10-08

申请号：AU2003223306

申请日：2003-03-19

Applicant: IBM

Inventor： NOWAK EDWARD J ,  CLARK WILLIAM F ,  LANZEROTTI LOUIS D ,  FRIED DAVID M

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.