公开(公告)号：JP2005094014A

公开(公告)日：2005-04-07

申请号：JP2004269168

申请日：2004-09-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DALTON TIMOTHY J ,  GATES STEPHEN M

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/02063 ,  H01L21/76814

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a BEOL interconnection structure provided with a plurality of via contacts each having low via-contact resistance on a semiconductor device. SOLUTION: The method includes steps of: forming a porous or dense low-k dielectric layer on a substrate; forming, in the low-k dielectric layer, an opening etched by means of a single or dual damascene process; arranging the substrate on a cold chuck at a temperature of about -200°C to about 25°C inside a process chamber; additively introducing a condensable cleaning agent into the process chamber to have a CCA layer condensed inside the etched opening on the substrate; and implementing an activation step while a wafer is cooled down to a temperature of about -200°C to about 25°C. This via contact is extremely stable during a temperature cycle and the operation of the semiconductor device. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造具有在半导体器件上具有低通孔接触电阻的多个通孔触点的BEOL互连结构的方法。 解决方案：该方法包括以下步骤：在衬底上形成多孔或致密的低k电介质层; 在低k电介质层中形成通过单镶嵌或双镶嵌工艺蚀刻的开口; 将衬底在处理室内的约-200℃至约25℃的温度下布置在冷卡盘上; 将可冷凝清洁剂加入到处理室中以使CCA层在衬底上的蚀刻开口内冷凝; 并且在将晶片冷却至约-200℃至约25℃的温度的同时实施激活步骤。 该通孔接触在温度循环和半导体器件的操作期间非常稳定。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004146800A

公开(公告)日：2004-05-20

申请号：JP2003313299

申请日：2003-09-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CANAPERI DONALD F ,  DALTON TIMOTHY J ,  GATES STEPHEN M ,  KRISHNAN MAHADEVAIYER ,  PURUSHOTHAMAN SAMPATH ,  SMITH SEAN P E ,  NITTA SATYA

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure which realizes high performance interconnection including copper wiring and an insulator having an extremely low dielectric constant (k). SOLUTION: In this structure, wiring is supported by a low-k dielectric material having relatively high durability, such as SiLk(R) or SiO 2 , and then the remaining spaces in the structure are filled with a gap filling dielectric material that has an extremely low-k and a small hardness. Accordingly, in the structure, durable layers for obtaining the strength are bonded with an extremely low-k dielectric material for achieving electric performance of the interconnection. As a result, damages to and an increase in dielectric constant of the extremely low-k dielectric material caused during the manufacturing process are avoided, and delamination in the structure during the metal chemical mechanical polishing processes is prevented. Further, photoresist poisoning troubles caused by interaction with the extremely low-k dielectric material can be removed. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2005236285A

公开(公告)日：2005-09-02

申请号：JP2005033943

申请日：2005-02-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GATES STEPHEN M ,  NGUYEN SON VAN

IPC: H01L21/768 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an improved BEOL interconnection structure that has a ULK (ultra-low k) dielectric. SOLUTION: This structure can be of a single or dual damascene type provided with high-density TDL (thin dielectric layer) between a metal barrier layer and the ULK dielectric. Further, a method of manufacturing a BEOL interconnection structure includes (i) a method of forming a high-density TDL in an opening of the ULK dielectric bored by etching, and (ii) a method of arranging the ULK dielectric in a process chamber on a cold chuck, putting a seal agent into the process chamber and further performing an activating step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有ULK（超低k）电介质的改进的BEOL互连结构。 解决方案：该结构可以是在金属阻挡层和ULK电介质之间提供高密度TDL（薄介电层）的单镶嵌或双镶嵌型。 此外，制造BEOL互连结构的方法包括：（i）在通过蚀刻钻孔的ULK电介质的开口中形成高密度TDL的方法，以及（ii）将ULK电介质布置在处理室中的方法 冷卡盘，将密封剂放入处理室中，并进一步执行激活步骤。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004080017A

公开(公告)日：2004-03-11

申请号：JP2003275624

申请日：2003-07-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GATES STEPHEN M ,  DALTON TIMOTHY J ,  PHIZHIMONS JOHN A

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a novel interconnecting structure possessing relatively low internal stress and a dielectric constant for use in semiconductor devices. SOLUTION: This structure is provided with at least one of each of a first interconnecting level 9 provided with a first layer 10, a second interconnecting level 28 provided with a second layer 30, and a stress adjustment cap layer 22 that is formed between the first layer 10 and the second layer 30. The first interconnecting level 9 is stacked. Each has a coefficient of thermal expansion greater than about 20ppm, and is provided with the first layer 10 having the first internal stress. The first layer 10 is provided with a first set of metal wires 14 that are formed in it. The second interconnecting level 28 is stacked. Each has a coefficient of thermal expansion less than about 20ppm, and is provided with the second layer 30 having the second internal stress. The second layer 30 is provided with a second set of metal wires 34 that are formed in it. The stress adjustment cap layer 22 is selected to offset the first internal stress of the first layer 10 and the second internal stress of the second layer 30. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000048340A

公开(公告)日：2000-02-18

申请号：JP21074199

申请日：1999-07-26

Applicant: IBM

Inventor： BLACK CHARLES T ,  GATES STEPHEN M ,  MURRAY CHRISTOPHER B ,  SUN SHOUHENG

IPC: G11B5/712 ,  G11B5/62 ,  G11B5/738 ,  G11B5/842 ,  H01F1/00 ,  H01F1/047

Abstract: PROBLEM TO BE SOLVED: To provide a method to form periodical arrangement of magnetic nano particles into a layer (which may be a single layer or multilayer) with high regularity and to stabilize the arrangement above described on a substrate. SOLUTION: Magnetic nano particles having substantially uniform diameter are arranged at substantially uniform interval on the surface of a substrate 5. The nano particles consist of a magnetic material selected from a group of elements of Co, Fe, Ni, Mn, Sm, Nd, Pr, Pt and Gd, intermetallic compds. of the above elements, binary alloys of the above elements, ternary alloys of the above elements, Fe oxides containing at least one kind of element above described except for Fe, barium ferrite and strontium ferrite. A wear-resistant coating film is preferably deposited so as to adhere the nano particles to the substrate 5 and to maintain the substantially uniform interval.

公开(公告)号：JP2011211175A

公开(公告)日：2011-10-20

申请号：JP2011044902

申请日：2011-03-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NGUYEN SON VAN ,  GRILL ALFRED ,  GATES STEPHEN M ,  VO TUAN ANH ,  DIMITRAKOPOULOS CHRISTOS ,  NEUMAYER DEBORAH ANN ,  DAMON B FARMER

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/786

CPC classification number: H01L29/1606 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7831

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure and electronic device, formed in high density, and having smaller structural dimensions and a more exact shape.SOLUTION: Semiconductor structures and electronic devices include at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including a carbon-based material.

Abstract translation: 要解决的问题：提供一种形成为高密度且具有较小结构尺寸和更精确形状的半导体结构和电子器件。解决方案：半导体结构和电子器件包括至少一层界面介电材料，位于 碳基材料的上表面。 所述至少一层界面介电材料具有与碳基材料相同的短程结晶结合结构，通常是六边形，因此至少一层界面介电材料不会改变 碳基材料的电子结构。 具有与碳基材料相同的短程结晶结合结构的至少一层界面介电材料的存在改善了碳基材料和任何覆盖材料层（包括介电材料）之间的界面结合， 导电材料或介电材料和导电材料的组合。 改进的界面结合又有助于形成包括碳基材料的装置。

公开(公告)号：JP2011082540A

公开(公告)日：2011-04-21

申请号：JP2010256739

申请日：2010-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GATES STEPHEN M ,  GRILL ALFRED

IPC: H01L21/312 ,  C09C1/00 ,  H01L21/316 ,  H01L21/768

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02277 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249953 ,  Y10T428/249978 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an ultra low dielectric constant (k) film having a dielectric constant of ≤2.7, with improved mechanical characteristics such as improved elastic modulus and hardness, and to provide a method of manufacturing the film. SOLUTION: The multiphase, ultra low k film 38 is provided which exhibits improved elastic modulus and hardness, along with various methods for forming the same. The multiphase, ultra low k dielectric film 38 includes atoms of Si, C, O and H, has a dielectric constant of ≤2.4, nanosized pores or voids, an elastic modulus of about 5 or greater and a hardness of about ≥0.7. A preferred multiphase, ultra low k dielectric film 38 includes atoms of Si, C, O and H, has a dielectric constant of about ≤2.2 or less, nanosized pores or voids, an elastic modulus of about ≥3 and hardness of about ≥0.3. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供介电常数≤2.7的超低介电常数（k）膜，具有改善的弹性模量和硬度等机械特性，并提供一种制造该膜的方法。 解决方案：提供多相超低k膜38，其具有改进的弹性模量和硬度，以及其形成方法的各种方法。 多相超低k电介质膜38包括Si，C，O和H的原子，介电常数≤2.4，纳米孔或空隙，弹性模量约5或更大，硬度约≥0.7。 优选的多相超低k介电膜38包括Si，C，O和H的原子，介电常数约≤2.2或更小，纳米孔或空隙，弹性模量约≥3，硬度约≥0.3 。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009044162A

公开(公告)日：2009-02-26

申请号：JP2008224431

申请日：2008-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GATES STEPHEN M ,  DIMITRAKOPOULOS CHRISTOS D ,  GRILL ALFRED ,  NGUYEN SON VAN

IPC: H01L21/312 ,  H01L21/768 ,  C23C16/00 ,  C23C16/40 ,  C23C16/56 ,  H01B3/46 ,  H01L21/31 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L21/02126 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a dielectric material containing elements of Si, C, O and H, having specific mechanical property values (tensile stress, elastic modulus, hardness, cohesive force, and crack speed in water) which provide stable ultralow-k film without deterioration arising from steam or integration processing. SOLUTION: The dielectric materials 34, 38 and 44 have dielectric constants of approximately 2.8 or less, tensile stress of less than 45 Mpa, elastic modulus of somewhere between 2 and 15 GPa, hardness between around 0.2 to 2 GPa. Additionally, an electronic device structure containing the dielectric materials and various methods for producing them are disclosed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供含有Si，C，O和H元素的电介质材料，其具有特定的机械性能值（拉伸应力，弹性模量，硬度，内聚力和水中的裂纹速度），其提供稳定的 超低k电影没有蒸汽或整合处理的劣化。 电介质材料34,38和44具有约2.8或更小的介电常数，小于45Mpa的拉伸应力，2至15GPa之间的弹性模量，约0.2至2GPa之间的硬度。 另外，公开了包含电介质材料的电子器件结构及其制造方法。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2003218109A

公开(公告)日：2003-07-31

申请号：JP2003003569

申请日：2003-01-09

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  ANAND MINAKSHISUNDARAN B ,  ARMACOST MICHAEL D ,  CHEN SHYNG-TSONG ,  GATES STEPHEN M ,  GRECO STEPHEN E ,  KARECKI SIMON M ,  NITTA SATYANARAYANA V

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a metallic pattern on a low-dielectric constant substrate. SOLUTION: A hard mask including a lower hard mask layer 31 and an upper hard mask layer 20 is prepared. The upper hard mask layer 20 is a sacrifice layer of about 200 Å thick, which is preferably made of high-melting-point nitride. The sacrifice layer functions as a stop layer in the following CMP metal removal process. A resist layer is used to perform patterning. A protection layer 31t is formed on a hard mask, or a non-oxidized resist strip process is used, so as to avoid the damage of oxidization to the lower hard mask layer 31. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000114453A

公开(公告)日：2000-04-21

申请号：JP27273198

申请日：1998-09-28

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  HWANG WEI ,  GATES STEPHEN M

IPC: G11C11/41 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/11 ,  H01L29/786 ,  H03K19/0944 ,  H03K19/0948 ,  H03K19/20

Abstract: PROBLEM TO BE SOLVED: To obtain a high-density and high-speed merged logic circuit using two semiconductor layers: a thin film and a bulk silicon water layer and to obtain a memory IC chip. SOLUTION: A memory cell uses a three-dimensional(3D) SRAM structure. Two types of 3D logic cells are disclosed. They are of DCVS (DCVSG) architecture in 3D form provided with differential cascade voltage switch(DCVS) architecture in 3D form and pass gate logic. An SRAM memory cell of PMOS transistors Q5 and Q6 with a large logic cell is placed inside a thin-film silicon layer 507. High-speed NMOS transistors Q1-Q4 are placed in a bulk silicon wafer layer 501. A high density is attained in this way.