公开(公告)号：JP2003273158A

公开(公告)日：2003-09-26

申请号：JP2003003619

申请日：2003-01-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FURMAN BRUCE KENNETH ,  SURENDRA MAHESWARAN ,  GOMA SHERIF A ,  KARECKI ANNA ,  KARECKI SIMON M ,  MAGERLEIN JOHN HAROLD ,  PETRARCA KEVIN SHAWN ,  PURUSHOTHAMAN SAMPATH ,  SAMBUCETTI CARLOS JUAN ,  VOLANT RICHARD PAUL ,  WALKER GEORGE FREDERICK

IPC: H01L23/52 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/60 ,  H05K1/03 ,  H05K1/11 ,  H05K3/38

CPC classification number: H01L24/12 ,  H01L21/288 ,  H01L21/2885 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13582 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: PROBLEM TO BE SOLVED: To provide a system making an interconnection with a quite high density by connecting device chips and a chip carrier by using a microjoint interconnect structure.
SOLUTION: In the system, a pair of device chips is mounted on a microjoint interconnect chip carrier by using a microjoint interconnect structure. The microjoint interconnect chip carrier comprises a multilayer substrate having a plurality of receptacles on its surface. A pair of microjoint interconnect pads corresponding to the receptacles is provided on the device chips. Interconnecting wiring enabling an interconnection between the device chips is provided between the receptacles.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：通过使用微型连接互连结构，通过连接器件芯片和芯片载体来提供使密度相当高的互连的系统。 解决方案：在系统中，通过使用微型连接互连结构将一对器件芯片安装在微型连接互连芯片载体上。 微型连接互连芯片载体包括其表面上具有多个插座的多层基板。 在器件芯片上设置一对对应于插座的微接点互连焊盘。 在插座之间设置能够实现器件芯片之间的互连的互连布线。 版权所有（C）2003，JPO

公开(公告)号：JP2003218109A

公开(公告)日：2003-07-31

申请号：JP2003003569

申请日：2003-01-09

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  ANAND MINAKSHISUNDARAN B ,  ARMACOST MICHAEL D ,  CHEN SHYNG-TSONG ,  GATES STEPHEN M ,  GRECO STEPHEN E ,  KARECKI SIMON M ,  NITTA SATYANARAYANA V

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a metallic pattern on a low-dielectric constant substrate. SOLUTION: A hard mask including a lower hard mask layer 31 and an upper hard mask layer 20 is prepared. The upper hard mask layer 20 is a sacrifice layer of about 200 Å thick, which is preferably made of high-melting-point nitride. The sacrifice layer functions as a stop layer in the following CMP metal removal process. A resist layer is used to perform patterning. A protection layer 31t is formed on a hard mask, or a non-oxidized resist strip process is used, so as to avoid the damage of oxidization to the lower hard mask layer 31. COPYRIGHT: (C)2003,JPO