公开(公告)号：DE2961692D1

公开(公告)日：1982-02-18

申请号：DE2961692

申请日：1979-08-07

Applicant: IBM

Inventor： HAJDU JOHANN ,  KNAUFT GUNTER

IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

Abstract: An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

公开(公告)号：DE2747304A1

公开(公告)日：1979-04-26

申请号：DE2747304

申请日：1977-10-21

Applicant: IBM DEUTSCHLAND

Inventor： BAZLEN DIETER DIPL ING DR ,  BERGER ROLF DIPL ING ,  BLUM ARNOLD DIPL ING ,  BOCK DIETRICH DIPL ING ,  CHILINSKI HERBERT DIPL ING ,  GENG HELLMUTH ROLAND ,  HAJDU JOHANN ,  IRRO FRITZ DIPL ING ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22 ,  G06F9/16 ,  G06F13/06

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：DE2134816A1

公开(公告)日：1973-02-01

申请号：DE2134816

申请日：1971-07-13

Applicant: IBM DEUTSCHLAND

Inventor： BOGER KLAUS ,  GOETZE VOLKMAR ,  GENG HELLMUTH R ,  HAJDU JOHANN

IPC: G06F12/10 ,  G06F13/06

Abstract: In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.

公开(公告)号：IT7925850D0

公开(公告)日：1979-09-20

申请号：IT2585079

申请日：1979-09-20

Applicant: IBM

Inventor： HAJDU JOHANN ,  KNAUFT GUENTER

IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C

Abstract: An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

公开(公告)号：DE2758146A1

公开(公告)日：1979-06-28

申请号：DE2758146

申请日：1977-12-27

Applicant: IBM DEUTSCHLAND

Inventor： BLUM ARNOLD DIPL ING ,  CHILINSKI HERBERT DIPL ING ,  GENG HELLMUTH ROLAND ,  GETZLAFF KLAUS ING GRAD ,  HAJDU JOHANN ,  NEUBER SIEGFRIED ,  RICHTER STEPHAN ,  RUST BERND ,  WILLE UDO ING GRAD

IPC: G06F9/38 ,  G06F9/00 ,  G06F13/06 ,  G11C7/00

Abstract: A control switching network is used in the programming circuit of a digital calculator. The processing unit is connected to a process timing and control unit. This unit is connected to a data store via a set of the intermediate connections. A system is used to keep the store in synchronism with the processing unit. An identification network is used, which produces a signal controlling the action of the store. Store activity monitoring signals are used, and instructions are given to the store in a series of given cycles.

公开(公告)号：FR2406851A1

公开(公告)日：1979-05-18

申请号：FR7828926

申请日：1978-10-02

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22 ,  G06F9/16

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：FR2280934A1

公开(公告)日：1976-02-27

申请号：FR7521458

申请日：1975-07-01

Applicant: IBM

Inventor： BLUM ARNOLD ,  HAJDU JOHANN ,  MOHR CLAUD ,  REICHL LEOPOLD ,  SONNTA GUNTHER

IPC: G06F9/22 ,  G06F13/12 ,  G06F13/14 ,  G06F15/16 ,  G06F15/78 ,  G06F15/00

Abstract: Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.

公开(公告)号：DE2246863A1

公开(公告)日：1974-04-11

申请号：DE2246863

申请日：1972-09-23

Applicant: IBM DEUTSCHLAND

Inventor： HAJDU JOHANN ,  HELKE HERMANN DIPL ING ,  VOGT EDWIN DR ING

IPC: G06F9/22 ,  G06F11/28 ,  G06F11/34 ,  G06F9/06

公开(公告)号：DE2150291A1

公开(公告)日：1973-04-19

申请号：DE2150291

申请日：1971-10-08

Applicant: IBM DEUTSCHLAND

Inventor： GENG HELLMUTH ,  HAJDU JOHANN ,  SKUIN PETAR DIPL ING

IPC: G06F7/00 ,  A63F7/02 ,  G06F5/01 ,  G06F7/76 ,  G11C19/00

Abstract: A circuit arrangement is provided for controlling a known logical switching network for shifting data of variable widths, wherein the shift amount by which the data bits applied to the input are to be shifted is switched from the true value to the complement value and vice versa by means of a control signal influenced by control commands, and wherein the partial results thus produced are logically combined to form a further partial result or the final result.

公开(公告)号：DE2140858A1

公开(公告)日：1973-03-08

申请号：DE2140858

申请日：1971-08-14

Applicant: IBM DEUTSCHLAND

Inventor： CHILINSKI HERBERT ,  GENG HELLMUTH ROLAND ,  HAJDU JOHANN

IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F11/10 ,  G11C19/00