公开(公告)号：DE69117916D1

公开(公告)日：1996-04-18

申请号：DE69117916

申请日：1991-12-09

Applicant: IBM

Inventor： GRILL ALFRED ,  HORNG CHENG TZONG ,  MEYERSON BERNARD STEELE ,  PATEL VISHNUBHAI VITTHALBHAI ,  RUSSAK MICHAEL ALLEN ,  CHANG HENRY CHINLIN ,  CHEN MAO-MIN ,  SCHWENKER ROBERT OTTO

IPC: G11B5/31 ,  G11B5/60

公开(公告)号：DE3279966D1

公开(公告)日：1989-11-02

申请号：DE3279966

申请日：1982-12-07

Applicant: IBM

Inventor： CHU SHAO-FU ,  HO ALLEN PANG-I ,  HORNG CHENG TZONG ,  KEMLAGE BERNARD MICHAEL

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate by forming a wide plug of chemical vapor deposited silicon dioxide in the trench, filling the remaining unfilled trench portions by chemical vapor depositing a layer of silicon dioxide over the substrate and etching back this layer. The method produces chemically pure, planar wide deep dielectric filled isolation trenches and may also be used to simultaneously produce narrow deep dielectric filled isolation trenches.

公开(公告)号：DE3168576D1

公开(公告)日：1985-03-14

申请号：DE3168576

申请日：1981-04-02

Applicant: IBM

Inventor： HORNG CHENG TZONG ,  KONIAN RICHARD ROBERT ,  SCHWENKER ROBERT OTTO ,  WIEDER ARMIN WILHELM

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L27/08 ,  H01L21/82

公开(公告)号：DE3167670D1

公开(公告)日：1985-01-24

申请号：DE3167670

申请日：1981-02-16

Applicant: IBM

Inventor： HORNG CHENG TZONG

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/331 ,  H01L21/60 ,  H01L21/762 ,  H01L29/73 ,  H01L29/732 ,  H01L21/00 ,  H01L21/285 ,  H01L29/72

Abstract: Disclosed is a self-aligned process for providing an improved high-performance bipolar transistor. The transistor device region is isolated from the other devices on the wafer by a wide deep oxide trench. The deep oxide trench which has nearly vertical sidewalls, extends from the epitaxial silicon surface through the N+ subcollector region into the P- substrate. A shallow oxide trench is used to separate the collector reach through region from the base region. A heavily doped polysilicon layer is used to dope and make contact to the transistor base as well as define the emitter window through which the emitter is doped. In the structure, the separation between the emitter contact and the polysilicon base contact is reduced to a very small value. This is achieved by employing the self-aligned process in accordance with the invention. Metal contact to the polysilicon base contact is done over the deep trench oxide isolation. This allows the transistor base area, and hence the collector base capacitance to be minimized. The shallow emitter and narrow base width of the transistor are formed by ion implantations.

公开(公告)号：DE68919461T2

公开(公告)日：1995-05-24

申请号：DE68919461

申请日：1989-08-03

Applicant: IBM

Inventor： BAJOREK CHRISTOPHER HENRY ,  HORNG CHENG TZONG ,  YEN EDWARD TSIANG-CHIEN

IPC: G11B5/39

Abstract: A shielded magnetoresistive (MR) sensor in which the first shield (12) is of sendust or super sendust and the second shield is of permalloy is made by the steps of depositing a layer of sendust or super sendust to form a first shield; heat treating the sendust layer at a temperature greater than 400 DEG C; depositing a first electrically insulating layer (18) ; depositing, in the presence of a magnetic field, a MR layer (20) ; depositing a second layer (26) of electrically insulating material; and, depositing a layer (28) of permalloy to form the second shield.

公开(公告)号：DE68919461D1

公开(公告)日：1995-01-05

申请号：DE68919461

申请日：1989-08-03

Applicant: IBM

Inventor： BAJOREK CHRISTOPHER HENRY ,  HORNG CHENG TZONG ,  YEN EDWARD TSIANG-CHIEN

IPC: G11B5/39

Abstract: A shielded magnetoresistive (MR) sensor in which the first shield (12) is of sendust or super sendust and the second shield is of permalloy is made by the steps of depositing a layer of sendust or super sendust to form a first shield; heat treating the sendust layer at a temperature greater than 400 DEG C; depositing a first electrically insulating layer (18) ; depositing, in the presence of a magnetic field, a MR layer (20) ; depositing a second layer (26) of electrically insulating material; and, depositing a layer (28) of permalloy to form the second shield.

公开(公告)号：DE3170791D1

公开(公告)日：1985-07-11

申请号：DE3170791

申请日：1981-02-05

Applicant: IBM

Inventor： HORNG CHENG TZONG ,  SCHWENKER ROBERT OTTO ,  TSANG PAUL JA-MIN

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L21/60 ,  H01L21/762 ,  H01L29/08 ,  H01L29/732 ,  H01L21/76 ,  H01L21/00 ,  H01L29/72

Abstract: Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer (10) to undercut another top layer (11) of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug (14) is formed to block the emitter region (12) from the heavy P+ ion dose implant of the extrinsic base (19).

公开(公告)号：DE3165481D1

公开(公告)日：1984-09-20

申请号：DE3165481

申请日：1981-02-25

Applicant: IBM

Inventor： HO ALLEN PANG-I ,  HORNG CHENG TZONG

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L29/417 ,  H01L29/732 ,  H01L21/00 ,  H01L21/285 ,  H01L21/60 ,  H01L21/76 ,  H01L29/72

公开(公告)号：DE3063331D1

公开(公告)日：1983-07-07

申请号：DE3063331

申请日：1980-08-12

Applicant: IBM

Inventor： HORNG CHENG TZONG ,  LILLJA HAROLD VINELL ,  SETO DAVID KENROKU

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/266 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L29/10 ,  H01L21/00