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    CIRCUIT FOR DELAY NORMALISATION OF INTERCONNECTED SEMICONDUCTOR CHIPS
    12.
    发明专利
    CIRCUIT FOR DELAY NORMALISATION OF INTERCONNECTED SEMICONDUCTOR CHIPS 未知

    公开(公告)号：DE3175288D1

    公开(公告)日：1986-10-16

    申请号：DE3175288

    申请日：1981-04-28

    Applicant: IBM

    Inventor： BERNDLMAIER ERICH ,  DORLER JACK ARTHER ,  MOSLEY JOSEPH MICHAEL ,  WEITZEL STEPHEN DOUGLAS

    IPC: H03K19/00 ,  G05F1/46 ,  G06F1/04 ,  G06F1/10 ,  H03K3/03 ,  H03K5/00 ,  H03K19/0175 ,  H03K19/086 ,  H03L7/089 ,  H03L7/099

    Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock).

    17.
    发明专利
    未知

    公开(公告)号：DE3784002D1

    公开(公告)日：1993-03-18

    申请号：DE3784002

    申请日：1987-09-22

    Applicant: IBM

    Inventor： EVEN JOHN FARLEY ,  MOSLEY JOSEPH MICHAEL

    IPC: H03K19/082 ,  H03K3/03 ,  H03K3/282 ,  H03L7/099 ,  H03L7/08

    Abstract: A voltage controlled oscillator is formed of a plurality of cascaded inverter stages in a ring configuration. Each inverter stage is a grounded emitter circuit having an active pull-stage in order to achieve a short stage delay. The frequency of the ring oscillator is determined by the number of inverter stages, and the gain is selectable by coupling an external control voltage to only certain of the inverters. The VCO may be fabricated on a single integrated circuit along with the other circuits necessary to form a phase locked loop or other frequency generation system.

    CURRENT CONTROLLED GATE
    19.
    发明专利
    CURRENT CONTROLLED GATE 未知

    公开(公告)号：DE3169190D1

    公开(公告)日：1985-04-11

    申请号：DE3169190

    申请日：1981-10-09

    Applicant: IBM

    Inventor： DORLER JACK ARTHUR ,  MOSLEY JOSEPH MICHAEL

    IPC: H03K19/018 ,  H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K19/086

    Abstract: A current controlled gate performing a NOR function utilizes a pair of transistors (T4, T5) acting as current mirrors that receive a DC bias through a large resistor (R B ). This bias occurs when an input transistor (T1, T2) is positive to insure that one of the current mirror transistors (T4, T5) will saturate when the input transistors (T1, T2) are "off" and the other will be driven into saturation when either of the input transistors (T1, T2) is "on". When all inputs are negative, one of the current mirror transistors (T4, T5) saturates thereby reducing the current to the input transistors (T1, T2) effectively to zero. The saturation results in the collector-base capacitance increasing very rapidly such that the input assumes the characteristics of a common emitter due to the large capacitance existing in the collector of the current mirror transistor (T4, T5). An active push-pull output is produced with a single collector path from input to output.

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