公开(公告)号：DE3788141D1

公开(公告)日：1993-12-23

申请号：DE3788141

申请日：1987-01-08

Applicant: IBM

Inventor： KAUFFMAN ARTHUR AMOS ,  MUHICH JOHN STEPHEN

IPC: G06F12/02 ,  G06F3/14 ,  G06F3/153 ,  G06F12/00 ,  G06T1/00 ,  G06T1/60 ,  G06T3/60 ,  G11C7/00 ,  G11C11/401 ,  G06F15/62

Abstract: A data display system having a memory circuit including a bit addressable binary data memory in which the data is stored in a plurality of dimensional directions and a circuit for accessing a group of the data in the memory in at least two of the dimensional directions and for moving the data to a different dimensional location while maintaining the data within the group. Also provided is a means for accessing the data by incrementally or decrementally addressing the data in at least one of the directions. The accessing circuitry is further used to perform bit block transfers of data within the memory. The accessing circuit also provides for horizontal or vertical access during a read operation while orthogonally rotating the data by 90 degrees during a following write operation.

公开(公告)号：BR8606362A

公开(公告)日：1987-10-13

申请号：BR8606362

申请日：1986-12-22

Applicant: IBM

Inventor： MUHICH JOHN STEPHEN ,  THORNLEY JOSEPH STODDARD

IPC: G06F3/048 ,  G06F3/14 ,  G09G5/00 ,  G09G5/08 ,  G09G1/00

Abstract: A cursor generation circuit for an image display system that includes a storing circuit for storing image data. The storing circuit includes a first port to provide access to the image data to the display system and a second port to provide access to the image data to a display device for displaying the image data. A combining circuit is further provided to combine the image data with cursor data in the storing circuit when the storing circuit is being accessed by the display device. However, the combining circuit removes the cursor data from the image data when the image data is being accessed by the display system through the first port.

公开(公告)号：DE19852457C2

公开(公告)日：2002-07-11

申请号：DE19852457

申请日：1998-11-13

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT PAUL ,  MUHICH JOHN STEPHEN

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03K5/153 ,  H03L7/089

Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.

公开(公告)号：DE69327288T2

公开(公告)日：2000-06-08

申请号：DE69327288

申请日：1993-09-20

Applicant: IBM

Inventor： MOORE CHARLES ROBERTS ,  MUHICH JOHN STEPHEN

IPC: G06F12/08 ,  G06F12/10 ,  G06F15/16 ,  G06F15/177

Abstract: Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by any processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor. Thus, a broadcast translation lookaside buffer invalidate (TLBI) instruction may only be executed by the other processors within a multiprocessor system if it has been accepted by all processors within the system. After initiating execution of a translation lookaside buffer invalidate (TLBI) instruction at all processors within the system, the execution of pending instructions is temporarily terminated until after the translation lookaside buffer invalidate (TLBI) instruction has been executed. Thereafter, the execution of instructions is suspended until all read and write operations within the memory queue have achieved coherency. Next, all suspended and/or prefetched instructions are refetched utilizing the modified translation lookaside buffer (TLB) to ensure that the address utilized is still valid.

公开(公告)号：DE3689691T2

公开(公告)日：1994-09-15

申请号：DE3689691

申请日：1986-12-12

Applicant: IBM

Inventor： MUHICH JOHN STEPHEN ,  THORNLEY JOSEPH STODDARD

IPC: G09G5/08 ,  G09G1/00

公开(公告)号：DE3788141T2

公开(公告)日：1994-05-11

申请号：DE3788141

申请日：1987-01-08

Applicant: IBM

Inventor： KAUFFMAN ARTHUR AMOS ,  MUHICH JOHN STEPHEN

IPC: G06F12/02 ,  G06F3/14 ,  G06F3/153 ,  G06F12/00 ,  G06T1/00 ,  G06T1/60 ,  G06T3/60 ,  G11C7/00 ,  G11C11/401 ,  G06F15/62

Abstract: A data display system having a memory circuit including a bit addressable binary data memory in which the data is stored in a plurality of dimensional directions and a circuit for accessing a group of the data in the memory in at least two of the dimensional directions and for moving the data to a different dimensional location while maintaining the data within the group. Also provided is a means for accessing the data by incrementally or decrementally addressing the data in at least one of the directions. The accessing circuitry is further used to perform bit block transfers of data within the memory. The accessing circuit also provides for horizontal or vertical access during a read operation while orthogonally rotating the data by 90 degrees during a following write operation.

公开(公告)号：DE3785064T2

公开(公告)日：1993-10-07

申请号：DE3785064

申请日：1987-01-13

Applicant: IBM

Inventor： KO MICHAEL ANTHONY ,  MUHICH JOHN STEPHEN

IPC: G06F3/153 ,  G09G1/00 ,  G09G1/04 ,  G09G1/16 ,  G09G5/18 ,  G09G5/36 ,  G09G5/39 ,  G09G5/42

公开(公告)号：DE69815201D1

公开(公告)日：2003-07-10

申请号：DE69815201

申请日：1998-03-06

Applicant: IBM

Inventor： FEISTE KURT ALAN ,  MUHICH JOHN STEPHEN ,  THATCHER LARRY EDWARD ,  WHITE STEVEN WAYNE

IPC: G06F9/38 ,  G06F12/00

Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.

公开(公告)号：GB2322718A

公开(公告)日：1998-09-02

申请号：GB9725995

申请日：1997-12-09

Applicant: IBM

Inventor： HICKS TROY NEAL ,  LE HUNG OUI ,  MUHICH JOHN STEPHEN ,  WHITE STEVEN WAYNE

IPC: G06F9/38

Abstract: A pre-execution queue PEQ 42 stores instructions for an information handling system, and schedules the issuing of these instructions to at least one execution cluster 54, 56, each comprising an early, 46, 50, and a late, 48, 52, execution unit. Each execution unit executes an instruction dispatched from PEQ 42, and generates and forwards a result to another unit for execution of a further instruction. This result data forwarding takes longer if it is between units of different clusters. In particular, a result from early unit 46 is available to late unit 48 in the same cluster 54 in the same clock cycle. The instruction scheduling takes into account this non-uniform forwarding of result data (for example, by "pairing" dependent instructions and issuing them to the same cluster), and ensures that only instructions whose operands are available are scheduled. PEQ 42 classifies and groups the instructions into buckets with associated selection priorities (fig. 6). Instructions can be dynamically reassigned to buckets in response to execution delays and priority conflicts.

公开(公告)号：CA2107056C

公开(公告)日：1998-06-23

申请号：CA2107056

申请日：1993-09-27

Applicant: IBM

Inventor： OEHLER RICHARD RAPHAEL ,  KAHLE JAMES ALLAN ,  MUHICH JOHN STEPHEN ,  SILHA EDWARD JOHN

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177

Abstract: A method and system are disclosed for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible 5 in associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and this change bit is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate including accessible fields the reference bit and change bit may be concurrently updated by multiple processors, increasing memory concurrency.