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    13.
    发明专利
    未知

    公开(公告)号：AT497419T

    公开(公告)日：2011-02-15

    申请号：AT07822113

    申请日：2007-10-31

    Applicant: IBM

    Inventor： DAUBENSPECK TIMOTHY HARRISON ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY PETER ,  MUZZY CHRISTOPHER DAVID

    IPC: B23K1/20 ,  B23K20/24 ,  H01L25/065

    Abstract: Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.

    14.
    发明专利
    未知

    公开(公告)号：AT477588T

    公开(公告)日：2010-08-15

    申请号：AT05808156

    申请日：2005-11-16

    Applicant: IBM

    Inventor： BURRELL LLOYD ,  CHEN HOWARD ,  HSU LOUIS ,  SAUTER WOLFGANG

    IPC: H01L21/48 ,  H01L23/14 ,  H01L23/538

    Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

    17.
    发明专利
    未知

    公开(公告)号：AT490552T

    公开(公告)日：2010-12-15

    申请号：AT07822110

    申请日：2007-10-31

    Applicant: IBM

    Inventor： DAUBENSPECK TIMOTHY HARRISON ,  MUZZY CHRISTOPHER DAVID ,  GAMBINO JEFFREY PETER ,  SAUTER WOLFGANG

    IPC: H01L23/31 ,  H01L23/485

    Abstract: Methods of forming wire and solder bonds are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer to the wire bond metal region; and forming the wire bond to the wire bond metal region. Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.

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