公开(公告)号：GB2502662B

公开(公告)日：2014-07-30

申请号：GB201303300

申请日：2013-02-25

Applicant: IBM

Inventor： GHAI SANJEEV ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  STUECHELI JEFFREY ,  WILLIAMS DEREK EDWARD ,  WILLIAMS PHILIP

IPC: G06F12/12 ,  G06F12/08

公开(公告)号：AT544115T

公开(公告)日：2012-02-15

申请号：AT08775366

申请日：2008-07-29

Applicant: IBM

Inventor： CLARK LEO ,  FIELDS JAMES ,  GUTHRIE GUY ,  STARKE WILLIAM ,  WILLIAMS DEREK ,  WILLIAMS PHILIP

IPC: G06F12/08

Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

公开(公告)号：AU2013217351B2

公开(公告)日：2016-04-28

申请号：AU2013217351

申请日：2013-01-22

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM

IPC: G06F9/00

Abstract: A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining, by a processor core, that the load instruction is resolved based upon receipt by the processor core of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating by the processor core, in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing by the processor core, in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.

公开(公告)号：GB2516083A

公开(公告)日：2015-01-14

申请号：GB201312417

申请日：2013-07-11

Applicant: IBM

Inventor： NORTH GERAINT ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  WILLIAMS PHILIP ,  SHEN HUGH ,  NAYAR NARESH

IPC: G06F12/08 ,  G06F9/455 ,  G06F11/14 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/109 ,  G06F12/12

Abstract: A system comprises a processor running a hypervisor for virtual machines (VMs), a cache, e.g. a write-back cache, and a memory storing VM images for a differential check-pointing failover technique. The cache comprises rows having a memory address, a cache line, and an image modification flag. The modification flag is set (430) when a cache line is modified (420) by a backed-up VM (425), for which an image is saved in memory, while hypervisor actions in privilege mode do not set the flag. Flagged cache lines addresses are written in a log of the memory upon eviction (440) or during periodic checkpoints. Replication of the VM image in another memory can be obtained by fetching the cache lines stored at the logged addresses. Using the modification bit flag instead of dirty bit tags ensures that modified cache lines are written to the log without being flushed at the same time.

公开(公告)号：GB2513509A

公开(公告)日：2014-10-29

申请号：GB201414381

申请日：2013-01-22

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM

IPC: G06F9/30 ,  G06F9/38

Abstract: A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining, by a processor core, that the load instruction is resolved based upon receipt by the processor core of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating by the processor core, in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing by the processor core, in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.

公开(公告)号：DE112013000891T5

公开(公告)日：2014-10-16

申请号：DE112013000891

申请日：2013-01-22

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM

IPC: G06F9/00

Abstract: Eine Technik zum Verarbeiten einer Befehlsfolge, die einen Sperrbefehl, einen Ladebefehl vor dem Sperrbefehl und einen nachfolgenden Speicherzugriffsbefehl nach dem Sperrbefehl enthält, beinhaltet ein Feststellen, durch einen Prozessorkern, dass der Ladebefehl auf der Grundlage des Empfangs, durch den Prozessorkern, einer frühesten Antwort einer guten kombinierten Antwort für eine Leseoperation abgearbeitet ist, die dem Ladebefehl und Daten für den Ladebefehl entspricht. Wenn das Ausführen des nachfolgenden Speicherzugriffsbefehls nicht vor dem Beenden des Sperrbefehls eingeleitet wird, beinhaltet die Technik ferner als Reaktion auf ein Feststellen, dass der Sperrbefehl beendet ist, ein Einleiten, durch den Prozessorkern, des Ausführens des nachfolgenden Speicherzugriffsbefehls. Wenn das Ausführen des nachfolgenden Speicherzugriffsbefehls vor dem Beenden des Sperrbefehls eingeleitet wird, beinhaltet die Technik ferner als Reaktion auf ein Feststellen, dass der Sperrbefehl beendet ist, ein Unterbrechen, durch den Prozessorkern, des Verfolgens des nachfolgenden Speicherzugriffsbefehls im Hinblick auf ein Ungültigmachen.

公开(公告)号：AU2013217351A1

公开(公告)日：2014-08-14

申请号：AU2013217351

申请日：2013-01-22

Applicant: IBM

Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM

IPC: G06F9/00

Abstract: A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining, by a processor core, that the load instruction is resolved based upon receipt by the processor core of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating by the processor core, in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing by the processor core, in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.

公开(公告)号：GB2502663A

公开(公告)日：2013-12-04

申请号：GB201303302

申请日：2013-02-25

Applicant: IBM

Inventor： GHAI SANJEEV ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  STUECHELI JEFFREY ,  WILLIAMS DEREK ,  WILLIAMS PHILIP

IPC: G06F12/12 ,  G06F12/08

Abstract: A deallocate request specifying a target address associated with a target cache line is sent from processor core to lower level cache; if the request hits, replacement order of lower level cache is updated such that the target is more likely to be evicted (e.g. making the target line least recently used [LRU]) in response to a subsequent cache miss. On a subsequent miss, the target line is cast out to the lower level cache with an indication that the line was deallocation request target (e.g. by setting a field in directory). The lower level cache may include load and store pipelines, with the deallocation request sent to the load pipeline. The deallocation may be executed at completion of dataset processing. Lower cache may include state machines servicing data requests, with retaining and updating performed without allocation of state machine/s to the request. A previous coherence state of the target may be retained. An interconnect fabric may connect processing units.