Abstract:
A micro-electromechanical switch (MEMS) having a deformable elastomeric element (1) which exhibits a large change in conductivity with a small amount of displacement. The deformable elastomeric element (1) is displaced by an electrostatic force that is applied laterally resulting in a small transverse displacement. The transversal displacement, in turn, pushes a metallic contact (7) against two conductive paths (5, 6), allowing passage of electrical signals. The elastomer (1) is provided on two opposing sids with embedded metallic elements (9, 10), such as impregnated metallic rods, metallic sheets, metallic particles, or conductive paste. Actuation electrodes (18, 8) are placed parallel to the conductive sides of the elastomer. A voltage applied between the conductive side of the elastomer and the respective actuation electrodes (18, 8) generate the electrostatic attractive force that compresses the elastomer (1), creating the transverse displacement that closes the MEMS. The elastomeric based MEMS extends the lifetime of the switch by extending fatigue life of the deformable switch elements.
Abstract:
A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate 40. The TSV structure is provided with two or more independent electrical conductors 50, 60 insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.
Abstract:
A micro-electromechanical (MEM) switch capable of inductively coupling and decoupling electrical signals is described. The inductive MEM switch consists of a first plurality of coils (20, 30) on a moveable platform (15) and a second plurality of coils (40, 50) on a stationary platform or substrate, the coils on the moveable platform being above or below those in the stationary substrate. Coupling and decoupling occurs by rotating or by laterally displacing the coils of the moveable platform with respect to the coils on the stationary substrate. Diverse arrangements or coils respectively on the moveable and stationary substrates allow for a multi-pole and multi-position switching configurations. The MEM switches described eliminate problems of stiction, arcing and welding of the switch contacts. The MEMS switches of the invention can be fabricated using standard CMOS techniques.
Abstract:
PROBLEM TO BE SOLVED: To provide a bipolar transistor having self-aligned raised extrinsic base silicide and emitter contact border. SOLUTION: The bipolar transistor exhibits the parasitic property which is more reduced than the parasitic property exhibited by a bipolar transistor which is not equipped with self-aligned silicide and a self-aligned emitter contact border. In a method of manufacturing the bipolar transistor structure, a block emitter polysilicon region is replaced with a conventional T-shaped emitter polysilicon. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a structure and a method for reducing thermal mechanical stress in stack and via. SOLUTION: An interconnection structure for a semiconductor device comprises an organic low-k (low specific dielectric constant) dielectric layer formed on a lower metallization. The via to be formed here is in this low-k dielectric layer, and combines a lower metallization line formed on the lower metallization level and an upper metallization line formed on an upper metallization level. This via is surrounded by structure collar selected from material with CTE that can protect the via from shearing force generated after the thermal expansion of the low-k dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a process for fabricating a metal/insulator/metal capacitor(MIM cap) structure in a semiconductor substrate efficiently at low cost. SOLUTION: A metal oxide layer 18 is formed on a deposited underlying metal layer 16 using an anode oxidation procedure, a second metal 20 is deposited thereon and planarized by chemical mechanical polishing or other procedure to fabricate a metal/insulator/metal capacitor structure in a semiconductor substrate. This process is not a conventional etching process for forming a capacitor structure but an extra process. This process is applicable to the field of damascene structure and can be used for forming a variety of capacitor structures while decreasing the number of mask layers required for formation.
Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing a metal structure encapsulated in a feature formed in a substrate. SOLUTION: A side wall and bottom surface of a feature are covered with a barrier layer, and the feature is filled with metal preferably by electrolytical plating. A recess is made in the metal, an upper surface of the metal is covered to deposit an additional barrier layer contacted with a first barrier layer. The additional barrier layer is planarized preferably by chemical mechanical polishing. This method can be used to manufacture an MIM capacitor. In this case, the encapsulated metal structure functions as a lower plate of the capacitor. A second substrate layer is deposited on an upper surface of the substrate and an opening is made in an upper surface of the encapsulated metal structure. A dielectric layer is deposited on the opening to thereby cover the encapsulated metal structure at the bottom of the opening. An additional layer acting as the upper plate of the capacitor is deposited to cover the dielectric layer and fill the opening. The dielectric layer and additional layer are planarized preferably by the CMP method.
Abstract:
PROBLEM TO BE SOLVED: To provide an electric plating method of a metal structure in a feature formed in a substrate. SOLUTION: A liner material 22 is adhered to an upper surface of the substrate and a bottom surface and a side wall of the feature 21. Next, a seed layer 23 is adhered onto the liner by the CVD. The seed layer is selectively removed from the upper surface of the substrate so that the seed layer is left behind only on the bottom surface of the feature. The metal is electrically plated by using this part of the seed layer so that the metal fills the feature. The upper surface is not electrically plated because the seed layer is removed from the upper surface of the substrate.
Abstract:
PROBLEM TO BE SOLVED: To provide an inductor and a method of forming the inductor. SOLUTION: The method of forming the inductor comprises (a) a step for providing a semiconductor substrate, (b) a step for forming a dielectric layer on the surface of the substrate, (c) a step for forming a lower trench in the dielectric layer, (d) a step for forming a resist layer on the surface of the dielectric layer, (e) a step for forming an upper trench which is aligned to the lower trench and whose bottom is opened for the lower trench in the resist layer, and (f) a step for completely filling the lower trench with a conductor and at least partially filling the upper trench with the conductor to form the inductor. The semiconductor structure includes the inductor including the upper surface, bottom surface and sidewall and a means that allows the inductor to be electrically contacted, the lower section of the inductor is extended by a distance that the lower section of the inductor is fixed in the dielectric layer formed on the substrate, and the upper section thereof is extended on the dielectric layer. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a method of forming a wire bond in an I/C chip. SOLUTION: This method comprises steps of: providing an I/C chip having a conductive pad for wire bonding and at least one dielectric material layer on the pad; forming an opening penetrating the dielectric material layer to expose a part of said pad; forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening; forming a seed layer on the first conductive layer, applying photoresist onto the seed layer; exposing the photoresist to light and developing the light-exposed photoresist; exposing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material inside the opening to expose the seed layer; coating at least one second conductive material layer on the seed layer inside the opening; and removing the first conductive layer on the dielectric layer around the opening. The present invention includes the structure obtained by the above method. COPYRIGHT: (C)2005,JPO&NCIPI