公开(公告)号：WO0201607A3

公开(公告)日：2002-05-23

申请号：PCT/US0120206

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

IPC: H01L21/8242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：WO2007082227A3

公开(公告)日：2008-09-25

申请号：PCT/US2007060317

申请日：2007-01-10

Applicant: IBM ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)

Abstract translation: 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。 这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。 第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

公开(公告)号：WO0188977A3

公开(公告)日：2002-06-13

申请号：PCT/US0115759

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARARUNI RAMA ,  SRINIVASAN RADHIKA ,  HO HERBERT ,  BEINTNER JOACHEN ,  LI YUJUN ,  LAROSA GIUSEPPE

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

Abstract translation: 提供半导体器件及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 氮化物衬垫形成在沟槽中。 电荷被困在氮化物衬垫中。 在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。 优选地，氧化物填充物直接形成在氮化物衬垫上。

公开(公告)号：WO0237542A2

公开(公告)日：2002-05-10

申请号：PCT/US0146921

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  KUDELKA STEPHAN

IPC: H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/10867 ,  H01L27/10876

Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.

Abstract translation: 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

公开(公告)号：WO2004066367A3

公开(公告)日：2009-05-28

申请号：PCT/US2004000968

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/76 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

Abstract: A low-GIRL current MOSFET device (90) structure and a method of fabrication thereof which provides a low-GIRL current. The MOSFET device structure contains a central gate conductor (10) whose edges may slightly overlap the source/drain diffusions (88, 88), and left and right side wing gate conductors (70,70) which are separated from the central gate conductor by a thin insulating and diffusion barrier layer (50, 52).

Abstract translation: 低GIRL电流MOSFET器件（90）结构及其制造方法，其提供低GIRL电流。 MOSFET器件结构包含中心栅极导体（10），其边缘可能与源极/漏极扩散（88,88）稍微重叠，并且左右翼栅极导体（70,70）与中心栅极导体分开， 薄的绝缘和扩散阻挡层（50,52）。

公开(公告)号：WO0199186A3

公开(公告)日：2002-10-10

申请号：PCT/US0119658

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUNKEL GERHARD ,  KOTECKI DAVID ,  PARK YOUNG JIN ,  GUTMANN ALOIS ,  MANDELMAN JACK A

IPC: H01L21/761 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/761

Abstract: A semiconductor device, in accordance with the present invention, includes a doped semiconductor substrate (102) wherein the doping of the substrate has a first conductivity and a device region (110) formed near a surface of the substrate. The device region includes at least one device well. A buried well (104) is formed in the substrate below the device region. The buried well is doped with dopants having a second conductivity. A trench region (124) surrounds the device region and extends below the surface of the substrate to at least the buried well such that the device region is isolated from other portions of the substrate by the buried well and the trench region.

Abstract translation: 根据本发明的半导体器件包括其中衬底的掺杂具有第一导电性的掺杂半导体衬底（102）和形成在衬底的表面附近的器件区（110）。 器件区域包括至少一个器件。 掩埋阱（104）形成在器件区域下方的衬底中。 掩埋阱掺杂具有第二导电性的掺杂剂。 沟槽区域（124）围绕器件区域并且在衬底的表面下方延伸到至少掩埋阱，使得器件区域通过掩埋阱和沟槽区域与衬底的其他部分隔离。

公开(公告)号：WO0201567A3

公开(公告)日：2002-02-25

申请号：PCT/US0120221

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841

公开(公告)号：JP2007243176A

公开(公告)日：2007-09-20

申请号：JP2007039055

申请日：2007-02-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TONTI WILLIAM R ,  MANDELMAN JACK A ,  HSU LOUIS LU-CHEN ,  WILLIAM P HOVIS ,  YANG CHIH-CHAO

IPC: H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electrically programmable fuse structure for IC, and its manufacturing method. SOLUTION: This electrically programmable fuse has a first terminal part and second terminal part that are interconnected with fuse and elements. The first terminal part and second terminal part exist in different heights to the support surface of the fuse structure. The interconnecting fuse element connects the height difference between the height of the first terminal part and the second terminal part. While the first terminal part and second terminal part are oriented to be parallel with the support surface, the fuse element include a part oriented to be a right angle to the support surface, and also include at least one right-angled curvature portion that connects at least one of the first terminal element and second terminal element and the part of the fuse element oriented to be right angle. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为IC提供电可编程熔丝结构及其制造方法。 解决方案：该电可编程熔丝具有与熔丝和元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分与熔丝结构的支撑表面存在不同的高度。 互连保险丝元件连接第一端子部分和第二端子部分的高度之间的高度差。 当第一端子部分和第二端子部分被取向为与支撑表面平行时，熔丝元件包括定向成与支撑表面成直角的部分，并且还包括至少一个直角曲率部分，其连接在 第一端子元件和第二端子元件中的至少一个和熔丝元件的一部分被定向为直角。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007150317A

公开(公告)日：2007-06-14

申请号：JP2006317746

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOBUZINSKY DAVID M ,  HO HERBERT L ,  MANDELMAN JACK A ,  OTANI YOICHI

IPC: H01L21/8247 ,  H01L21/265 ,  H01L21/76 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is formed in a semiconductor-on-insulator (SOI) substrate. SOLUTION: A memory cell comprises: a semiconductor-on-insulator substrate including a top semiconductor layer and a bottom semiconductor layer that are separated from each other by a buried insulating layer; and at least one vertical trench SONOS memory cell located in the semiconductor-on-insulator substrate. The at least one vertical trench SONOS memory cell comprises: a source diffusion located beneath the vertical trench; a selection gate channel located on one side of the vertical trench; an outward-diffused/Si-containing bridge located on and in contact with the selection gate channel; and a silicided doped region located adjacent to and in contact with an upper portion of the bridge. The bridge is present in the top semiconductor layer, the buried insulating layer, and the bottom semiconductor layer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元。 解决方案：存储单元包括：绝缘体上半导体衬底，包括通过掩埋绝缘层彼此分离的顶部半导体层和底部半导体层; 以及位于绝缘体上半导体衬底中的至少一个垂直沟道SONOS存储器单元。 所述至少一个垂直沟道SONOS存储单元包括：位于垂直沟槽下方的源极扩散; 位于所述垂直沟槽的一侧上的选择栅极沟道; 位于选择栅极通道上并与选择栅极通道接触的向外扩散/含Si桥; 以及位于与桥的上部相邻并与其接触的硅化物掺杂区域。 该桥存在于顶部半导体层，埋入绝缘层和底部半导体层中。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004193588A

公开(公告)日：2004-07-08

申请号：JP2003389984

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEWIS L SUU ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: G11C11/412 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM cell design capable of simultaneously attaining high performance, low power, and small chip size by using only vertical MOSFET device including a peripheral (transmission) gate. SOLUTION: A method for forming a SRAM cell device comprises the steps of forming a pass gate FET transistor in a silicon layer formed on a flat insulating material and a parallel island, and further forming a pair of vertical pulldown FET transistors having a first common body and a first common source region. The method further forms a pulldown separation space for dividing an upper layer of a pullup and pulldown drain region of a pair of vertical pulldown FET transistor in two by etching through the upper diffusion between cross-linked inverter FET transistors, and the separation space reaches the common boby layer. The method further comprises the steps of forming a pair of vertical pullup FET transistor having a second common body and a second common drain, and connecting the FET transistor so as to form a SRAM cell. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：通过仅使用包括外围（传输）门的垂直MOSFET器件，提供能够同时获得高性能，低功率和小芯片尺寸的SRAM单元设计。 解决方案：一种用于形成SRAM单元器件的方法包括以下步骤：在形成于平坦绝缘材料和平行岛上的硅层中形成栅极FET晶体管，并进一步形成一对垂直下拉FET晶体管，其具有 第一共同体和第一共同源区。 该方法进一步形成一个下拉分离空间，用于通过在交联的反相FET晶体管之间的上部扩散进行蚀刻，将一对垂直下拉式FET晶体管的上拉和下拉漏极区的上层分成两层，分离空间达到 普通boby层。 该方法还包括以下步骤：形成具有第二公共体和第二公共漏极的一对垂直上拉FET晶体管，并连接FET晶体管以形成SRAM单元。 版权所有（C）2004，JPO＆NCIPI