公开(公告)号：DE10143650A1

公开(公告)日：2003-03-13

申请号：DE10143650

申请日：2001-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  LUETZEN JOERN ,  POPP MARTIN ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory cell has trenches (25,50) in a substrate (15) having a capacitor (30) and long trenches having spacer wordlines with an active region between them having a vertical select transistor. Conductive bridges between wordlines in a trench are less than half as thick as the trench width. An Independent claim is also included for a process for making the above memory.

公开(公告)号：DE19941401C1

公开(公告)日：2001-03-08

申请号：DE19941401

申请日：1999-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND

IPC: H01L27/108 ,  H01L21/8242

Abstract: The invention relates to a DRAM cell arrangement. A cavity (V) for a capacitor of a storage cell pertaining to the DRAM cell arrangement is produced in a substrate (1). An insulation (I) and a storage node (SP) of the capacitor are generated in the cavity (V). A spacer consisting of silicon is produced over the storage node (SP). A first component of the spacer is doped by means of inclined implantation. The spacer is structured by using the different doping of the first component of the spacer. The storage node (SP) and the insulation (I) are changed by means of the structured spacer as a mask in such a way that the storage node (SP) is only directly adjacent to the substrate in a defined section of a flank pertaining to the cavity (V) and is otherwise separated from the substrate (1) by means of the insulation (I).

公开(公告)号：DE10131709B4

公开(公告)日：2006-10-26

申请号：DE10131709

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN

IPC: H01L21/8242 ,  H01L21/3213

Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.

公开(公告)号：DE102004026000A1

公开(公告)日：2005-02-24

申请号：DE102004026000

申请日：2004-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NUETZEL JOACHIM ,  MUEMMLER KLAUS ,  MANGER DIRK ,  SCHLOESSER TILL ,  WEIS ROLF ,  GOEBEL BERND ,  MUELLER WOLFGANG

IPC: G11C11/34 ,  H01L21/8242 ,  H01L27/108

Abstract: A cell field comprises memory cells (2) having lower source/drain regions (33) with sections of a trenched source/drain layer (332) perforated by perforated trenches (20) and word line trenches (7). An independent claim is also included for the production of a cell field.

公开(公告)号：DE59809504D1

公开(公告)日：2003-10-09

申请号：DE59809504

申请日：1998-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  BERTAGNOLLI EMMERICH ,  WILLER JOSEF ,  HASLER BARBARA ,  VON BASSE PAUL-WERNER

IPC: H01L21/8244 ,  H01L27/11

公开(公告)号：DE59904972D1

公开(公告)日：2003-05-15

申请号：DE59904972

申请日：1999-07-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  JACOBS HERMANN ,  SCHWARZL SIEGFRIED ,  BERTAGNOLLI EMMERICH

IPC: G11C11/14 ,  G11C11/00 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22

Abstract: A storage cell is described which includes a storage element whose electric resistance represents an information unit and can be influenced by a magnetic field as well as a transistor which when the information is read out allows for the corresponding storage cell to be selected from among the storage cells. To write the information unit, a write line and a bit line are provided which intersect in the area of the storage element and are able to generate the magnetic field. The storage cell is disposed between the bit line and a shared voltage supply connection. The storage cell is disposed between the bit line and the write line and the write line can coincide with a gate line that controls the transistor. The transistor is a planar or vertical transistor. The storage element and the transistor can be positioned next to or on top of each other.

公开(公告)号：DE10115912A1

公开(公告)日：2002-10-17

申请号：DE10115912

申请日：2001-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  MOL PETER ,  SEIDL HARALD ,  GUTSCHE MARTIN

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/8242 ,  H01L21/027 ,  H01L21/32 ,  H01L21/3213 ,  B81C1/00

Abstract: The invention relates to a lithographic method for removing a thin masking layer, particularly a Si3N4 layer on a side of a recess in a semi-conductor arrangement. According to the invention, an ion beam is orientated in an inclined manner at a certain angle towards the recess, enabling the thin masking layer to be removed in the regions exposed to the beams.

公开(公告)号：DE10362018A1

公开(公告)日：2005-01-20

申请号：DE10362018

申请日：2003-02-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  MANGER DIRK ,  GOEBEL BERND

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

Abstract: The arrangement has rows and columns separated by trenches (5,6) in a transistor cell field in a substrate, active regions (3) between upper (4) and lower (2) source/drain connection regions forming channels controllable by gate electrode potentials. The active regions join at least transistor cells (81) adjacent in the x-direction and charge transport is enabled between the active regions of transistor cells that are adjacent at least in the x-direction. An independent claim is also included for the following: (a) a method of manufacturing vertical transistor cells in a transistor cell field.

公开(公告)号：DE10131709A1

公开(公告)日：2003-01-30

申请号：DE10131709

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN

IPC: H01L21/3213 ,  H01L21/8242

Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.

公开(公告)号：DE10038728A1

公开(公告)日：2002-02-21

申请号：DE10038728

申请日：2000-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

IPC: H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory cell configuration includes dynamic memory cells respectively having a trench capacitor and a vertical selection transistor, the memory cells being disposed in matrix form, the trench capacitors and the associated vertical selection transistors following one another in each case in the form of rows and/or columns.