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    12.
    发明专利
    未知

    公开(公告)号：DE10139515A1

    公开(公告)日：2003-03-06

    申请号：DE10139515

    申请日：2001-08-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  LINDOLF JUERGEN

    IPC: G05F3/30 ,  H01L29/732 ,  H01L29/73 ,  H01L23/58 ,  G05F3/22

    Abstract: A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

    13.
    发明专利
    未知

    公开(公告)号：DE10107666C1

    公开(公告)日：2002-08-14

    申请号：DE10107666

    申请日：2001-02-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： AYADI KAMEL ,  MUELLER JOCHEN ,  LINDOLF JUERGEN ,  SAVIGNAC DOMINIQUE ,  DANKOWSKI STEFAN ,  LEHR MATTHIAS UWE ,  BRINTZINGER AXEL ,  FREY ULRICH

    IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

    Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15') above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15') in order to uncover the surface of the first insulating layer (25); forming a contact (11a') in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15'); and providing an interconnect (40a) for electrical connection of the contact (11a').

    14.
    发明专利
    未知

    公开(公告)号：DE10254160B4

    公开(公告)日：2006-07-20

    申请号：DE10254160

    申请日：2002-11-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KOWALSKI BERNHARD ,  FELBER ANDREAS ,  ROSSKOPF VALENTIN ,  SCHLOESSER TILL ,  LINDOLF JUERGEN

    IPC: H01L27/108 ,  G11C11/40 ,  H01L21/8242 ,  H01L27/02 ,  H01L29/94

    Abstract: A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

    15.
    发明专利
    未知

    公开(公告)号：DE50011761D1

    公开(公告)日：2006-01-05

    申请号：DE50011761

    申请日：2000-06-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LE THOAI-THAI ,  LINDOLF JUERGEN

    IPC: H01L21/82 ,  H01L23/525

    Abstract: A semiconductor configuration is described which includes a semiconductor body having a main surface and an insulator layer disposed on the main surface of the semiconductor body. The insulator layer has a cavity formed therein extending to the main surface of the semiconductor body. A fuse having a fusible part extends from the main surface of the semiconductor body toward an upper surface of the insulator layer at right angles to the main surface of the semiconductor body, and the fuse is embedded in the cavity. A method for producing the semiconductor configuration having the fuse is also described.

    17.
    发明专利
    未知

    公开(公告)号：DE10131388B4

    公开(公告)日：2004-07-08

    申请号：DE10131388

    申请日：2001-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LE THOAI-THAI ,  LINDOLF JUERGEN

    IPC: G11C29/00

    Abstract: An integrated dynamic memory includes a memory cell array having memory cells each assigned to one of a plurality of groups. The plurality of groups are divided into defect-free groups having exclusively defect-free memory cells and into defective groups having at least one defective memory cell. The memory further includes a memory configuration table that contains a list of the defect-free groups and an assignment unit that, based upon the entries in the memory configuration table, executes memory accesses only to those memory cells assigned to a defect-free group. The total capacity of the memory module, then, is not fixed once and for all with fabrication, but, rather, results only after a memory test, or may even vary in the course of the module lifetime.

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