公开(公告)号：DE10030445A1

公开(公告)日：2002-01-10

申请号：DE10030445

申请日：2000-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS RENE ,  LEIBERG WOLFGANG ,  RUF ALEXANDER ,  LEHR MATTHIAS ,  DRESCHER DIRK

IPC: H01L23/525

Abstract: The connection element in an integrated circuit has a layer structure arranged between two conductive structures. The layer structure has a dielectric layer which can be destroyed by application of a predetermined voltage. At least one conductive structure is composed of tungsten. The conductive structure adjoins a conductive layer made of tungsten or a tungsten compound, which is a constituent part of the layer structure and which adjoins the dielectric layer.

公开(公告)号：DE102006019962A1

公开(公告)日：2007-11-08

申请号：DE102006019962

申请日：2006-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUF ALEXANDER

IPC: B81C99/00

公开(公告)号：DE19922557B4

公开(公告)日：2004-11-04

申请号：DE19922557

申请日：1999-05-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMIDBAUER SVEN ,  RUF ALEXANDER

IPC: C23C14/06 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205

Abstract: A method for depositing a two-layer diffusion barrier on a semiconductor wafer consisting of a TaN layer and a Ta layer serving as a carrier layer for copper interconnects. The TaN layer is inventively deposited at temperatures above 200° C. in a first step, and the Ta layer is deposited in a second step while cooling the semiconductor wafer to a temperature below 50° C.

公开(公告)号：DE10208714A1

公开(公告)日：2003-09-25

申请号：DE10208714

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEEGANS MANFRED ,  RUF ALEXANDER

IPC: G11C5/06 ,  H01L21/283 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L31/0336

Abstract: Contact for an integrated circuit comprises entirely of titanium and/or titanium nitride. The contact runs through a contact hole in an insulation layer (5) between a first line plane and a second line plane to connect the first line plane to the second line plane. An Independent claim is included for a method for fabricating a contact, comprising depositing a titanium layer on the walls of the contact hole and on the surrounding surface of the insulation layer; depositing a titanium nitride layer in order to fill the contact hole and on the surrounding surface of the insulation layer; and polishing back titanium layer and the titanium nitride layer on the surrounding surface of the insulation layer in a single-stage polishing step.

公开(公告)号：DE19958202C2

公开(公告)日：2003-08-14

申请号：DE19958202

申请日：1999-12-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUF ALEXANDER ,  NICHTERWITZ MARION

IPC: C25D7/12 ,  C25D21/12 ,  C25D5/00 ,  C25D5/34 ,  C25D5/48

Abstract: A method for producing a metal layer with a given thickness includes the step of measuring an electrical resistance of the metal layer via connections on a starting layer provided under the metal layer. The resistance measurement is performed during or after the deposition of the metal layer. The layer thickness of the deposited metal layer is determined from the resistance measurement. Depending on the thickness of the already deposited metal layer, the deposition process is continued or repeated until a metal layer with a desired thickness is produced.

公开(公告)号：DE10153619A1

公开(公告)日：2003-05-15

申请号：DE10153619

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRUENING VON SCHWERIN ULRIKE ,  RUF ALEXANDER ,  RICHTER FRANK ,  BEWERSDORFF-SARLETTE ULRIKE

IPC: H01L21/336 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423

Abstract: The production of a gate layer stack for an integrated circuit configuration comprises depositing a lower gate layer on the gate oxide layer formed on a semiconductor substrate; depositing and patterning an upper gate layer; patterning an upper part of a layer thickness of the lower gate layer; depositing a protective layer; and further patterning until lower part of layer thickness is patterned. The production of a gate layer stack (10) for an integrated circuit configuration comprises depositing a lower gate layer on the gate oxide layer (2) formed on a semiconductor substrate (1); depositing an upper gate layer having a higher electrical conductivity than the lower gate layer above the lower gate layer; patterning at least the upper gate layer; patterning an upper part of a layer thickness of the lower gate layer; depositing a protective layer at least onto sidewalls (8) of the patterned upper gate layer and of the upper part of the layer thickness of the lower gate layer resulting in a formation of sidewall coverings (9), the lower gate layer, upper gate layer, and the protective layer defining the gate layer stack; and further patterning the gate layer stack at least until the gate oxide layer is reached and the lower gate layer is patterned only in a lower part of the layer thickness.

公开(公告)号：DE10136854A1

公开(公告)日：2003-02-20

申请号：DE10136854

申请日：2001-07-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KERSCH ALFRED ,  RUF ALEXANDER

IPC: C23C14/54

Abstract: The metal atoms and ions in the argon plasma are transported on a substrate (2). The coverage of the edge of the substrate hole with titanium layers (1a,1b), is verified experimentally by imaging the titanium layers. The result of the verification is compared with the compiled variant tables of relevant simulated deposition parameters for the substrate hole.

公开(公告)号：DE10010821A1

公开(公告)日：2001-09-13

申请号：DE10010821

申请日：2000-02-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUF ALEXANDER ,  KEGEL WILHELM ,  KARCHER WOLFRAM ,  SCHREMS MARTIN

IPC: H01L21/02 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: Increasing the capacity in a storage trench comprises depositing a first silicon oxide layer (4) in the trench; depositing a silicon layer (5) over the first layer to sufficiently cover the wall of the trench; and depositing a layer (6) containing an oxidizable metal. The silicon layer and the oxidizable metal layer are oxidized to form a layer containing a metal oxide and silicon oxide. An independent claim is also included for a trench capacitor comprising an inner wall covered with a silicon oxide layer which is covered with a metal oxide layer followed by a further silicon oxide layer. The remainder of the trench is filled with silicon. Preferred Features: Deposition is carried out by CVD or atomic layer deposition. The oxidizable metal is Ti, TiN, W, WN, Ta, TaN, WSi, TiSi or TaSi. Oxidation is carried out in an oxygen-containing atmosphere.