公开(公告)号：DE10140344A1

公开(公告)日：2003-03-06

申请号：DE10140344

申请日：2001-08-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  NIKUTTA WOLFGANG ,  BORCKE MATHIAS VON ,  KANDOLF HELMUT

IPC: H03K5/01 ,  H03K17/16 ,  H03K17/693 ,  H03K5/12 ,  H03K6/04

Abstract: The signal driver (100) has a first unit (102) for driving the signal (Vout) from first level in direction to a second level and a line of intermediate levels, contg. an intermediate level different from a reference level. The reference level lies between the first and second signal levels. A second unit (106) drives the signal in the direction of the second signal level from the last intermediate level of the line of intermediate levels. Independent claims are included for integrated circuit contg. the signal driver.

公开(公告)号：DE10125597A1

公开(公告)日：2002-12-12

申请号：DE10125597

申请日：2001-05-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GALL MARTIN ,  MUFF SIMON ,  SCHAEFER ANDRE

IPC: G11C5/00 ,  H05K1/02 ,  G06F13/38 ,  G11C7/00

Abstract: Data transmission network for transmission of data from and to memory chips mounted on a memory module circuit board. The inventive network is designed so that the resistance of a conducting section (6) upstream of a network node (7) is equal to the resistance of all the conducting sections downstream of the node, that in effect form parallel resistances.

公开(公告)号：DE102006019749A1

公开(公告)日：2007-07-19

申请号：DE102006019749

申请日：2006-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  BROX MARTIN

IPC: G11C11/406

Abstract: The method involves determining a temperature level of a memory module. The determined temperature level is compared with a reference temperature level of the module. Temporal distance of a refresh command transmitted from a control device e.g. memory controller (23), to another control device e.g. internal refresh controller (24), is changed during a variation between the temperature values to adjust cyclic refreshing of the cell to temperature of the memory module. The transmission of the command is stopped during the determined temperature level. Independent claims are also included for the following: (1) a device for adjustment of cyclic reconditioning of memory cells of a memory module to temperature of the memory module (2) a memory comprising a memory module.

公开(公告)号：DE10214101B4

公开(公告)日：2007-05-31

申请号：DE10214101

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL JOACHIM ,  SCHAEFER ANDRE

IPC: G11C11/406 ,  G11C7/04 ,  G11C11/4076 ,  H03K3/0231 ,  H03K3/0232 ,  H03L7/00

Abstract: The device has a capacitor, a differential current source for providing a capacitor charging current with temperature dependent and temperature independent current sources connected together so the current level of the capacitor charging current is proportional to the difference between the temperature dependent and temperature independent currents. A comparator outputs a refresh signal if the capacitor voltage exceeds a reference voltage. The device has a capacitor (C), a differential current source (14) for providing a capacitor charging current for charging the capacitor with temperature dependent and temperature independent current sources that are connected together so that the current level of the capacitor charging current is proportional to the difference between the temperature dependent and temperature independent currents. A comparator (12) outputs a refresh signal if the capacitor voltage (VC) exceeds a reference voltage (VREF). AN Independent claim is also included for the following: an arrangement for implementing the inventive method of producing a refresh signal for a memory cell of a semiconducting memory device, preferably a DRAM memory.

公开(公告)号：DE10244516B4

公开(公告)日：2006-11-16

申请号：DE10244516

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  SZCZYPINSKI KAZIMIERZ ,  POLNEY JENS

IPC: H03K19/0175 ,  G11C7/06 ,  H03K19/00 ,  H03K19/0185

Abstract: An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.

公开(公告)号：DE102005013237A1

公开(公告)日：2006-09-28

申请号：DE102005013237

申请日：2005-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  HEIN THOMAS ,  WEIS CHRISTIAN

IPC: G11C7/22 ,  G11C11/407

Abstract: The device has a timer which is a digital counter which counts the periodic counter pulse derived from a clock pulse in a circuit memory (1). The counter reports the end of a holding time between operations in the memory, when a desired number of pulses are counted. An adjusting unit in a mode register (40), is provided over an external connection of the circuit memory in order to adjust the desired number of pulses.

公开(公告)号：DE102004051958A1

公开(公告)日：2006-05-04

申请号：DE102004051958

申请日：2004-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE

IPC: G11C11/4072

Abstract: A circuit arrangement for adjusting selected operating parameters via a command input (CPO:3) for receiving external operating commands and further terminals (DPO:3, APO;13) for input and output of memory data. A register arrangement (VRO:7) is activated by a control signal and for each element it contains a value register for a number of M different operating parameters and for storing an inputted value information for the relevant parameter. A first group (GZ) of the adjustment information terminals is dedicated to the input of target information, A selection device (20) is provided for control of inputted target information through the first group of terminals. An independent claim is included for a method for using a circuit arrangement.

公开(公告)号：DE102004047663A1

公开(公告)日：2006-04-13

申请号：DE102004047663

申请日：2004-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE

IPC: G11C7/00 ,  G11C7/22 ,  G11C17/00

Abstract: The invention relates to a memory circuit comprising a read only memory unit for providing a number of fixed programmed test data; comprising an initialization unit in order, in an initialization mode, to output the fixed programmed test data in a specific sequence to an output terminal.

公开(公告)号：DE102004041961B3

公开(公告)日：2006-03-30

申请号：DE102004041961

申请日：2004-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE

IPC: H01L23/50 ,  H01L21/66 ,  H01L23/535

Abstract: An integrated semiconductor circuit comprises a substrate with a circuit, a plurality of wiring planes that are isolated from one another and from the substrate by insulator layers, and a signal path for the circuit in the substrate and/or the wiring planes. A first contact terminal, which is formed from a stack of metal areas in a plurality of the wiring planes, is designed for connecting the signal path to an external signal source or an external signal receiver during a test of the integrated semiconductor circuit. A second contact terminal, which is formed from a metal area or from a stack of metal areas in a plurality of wiring planes, is designed for connecting the signal path to an external signal source or an external signal receiver during normal operation of the integrated semiconductor circuit. The distance between the metal area or the bottommost metal area of the stack of the second contact terminal and the substrate is greater than the distance between the bottommost metal area of the stack of the first contact terminal and the substrate.

公开(公告)号：DE10121241B4

公开(公告)日：2005-07-07

申请号：DE10121241

申请日：2001-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUFF SIMON ,  GALL MARTIN ,  SCHAEFER ANDRE ,  BRAUN GEORG

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/50 ,  H01L23/66

Abstract: An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit, each connecting pin connected by an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit, where to minimize the line lengths of the associated wiring lines, the connecting pins to be connected to signal lines for high-frequency signals are fitted centrally to the housing.