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    11.
    发明专利
    未知

    公开(公告)号：DE50114869D1

    公开(公告)日：2009-06-10

    申请号：DE50114869

    申请日：2001-03-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LACHNER RUDOLF ,  SCHWERD MARKUS ,  SCHRENK MICHAEL

    IPC: H01G4/33 ,  H01L21/02 ,  H01L29/92 ,  H01L23/522

    Abstract: The integrated component has a number of conductor paths (13) and a capacitor (12) with a dielectric layer (5) between 2 electrode layers (14,15), which together are provided using the same sequence of metallisation layers (3,4,7-11) as that for the adjacent conductor path. The capacitor electrode layers may each be coupled to an underlying or overlying metal conductor path layer via a perpendicular connection (2,16), e.g. formed in an underlying intermediate dielectric layer (1).

    12.
    发明专利
    未知

    公开(公告)号：DE102005045060B4

    公开(公告)日：2007-07-05

    申请号：DE102005045060

    申请日：2005-09-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHWERD MARKUS ,  KOERNER HEINRICH ,  HOMMEL MARTINA ,  SECK MARTIN

    IPC: H01L23/522 ,  H01L21/768 ,  H01L27/08

    Abstract: The substrate (20) integrates semiconductor components. There are three circuit planes. These are designated close, intermediate or remote, with respect to the substrate, i.e. their spacing from the substrate increases with each layer. Each circuit plane contains a planar base surface and a planar covering surface adjoining a dielectric. The base surface of the circuit plane remote from the substrate (76), extends in a plane occupied by the covering surface of the intermediate circuit plane. Alternatively the base surface of the circuit plane remote from the substrate, extends in a plane lying closer to the substrate than a plane occupied by the covering surface of the intermediate circuit plane. In addition, the base surface of the intermediate circuit plane extends in a plane occupied by the covering surface of the circuit plane near the substrate. Alternatively the base surface of the intermediate circuit plane extends in a plane closer to the substrate than that occupied by the covering surface of the circuit plane close to the substrate. Circuit elements in the structure are further elaborated. A component formed by the elements (A-G), comprises one, two or more windings of a coil, a side wall of a coaxial line or parts of a condenser exceeding 10 mu m or 50 mu m in length. Salient features include use of aluminum or copper to form the tracks (34-38), at 60 atom% concentrations. They form internal conductors of the circuit (10). An even more remote conductive structure is included. One or more further circuit planes are included between the substrate and the circuit plane closest to it. An independent claim is also included for the method of manufacture.

    17.
    发明专利
    未知

    公开(公告)号：DE10337569A1

    公开(公告)日：2005-03-24

    申请号：DE10337569

    申请日：2003-08-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HELNEDER JOHANN ,  GOEBEL THOMAS ,  SCHWERD MARKUS ,  MITCHELL ANDREA ,  KOERNER HEINRICH ,  SECK MARTIN ,  DREXL STEFAN ,  KLEIN WOLFGANG ,  HOMMEL MARTINA

    IPC: H01L23/485 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

    19.
    发明专利
    未知

    公开(公告)号：AT430380T

    公开(公告)日：2009-05-15

    申请号：AT01913848

    申请日：2001-03-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LACHNER RUDOLF ,  SCHWERD MARKUS ,  SCHRENK MICHAEL

    IPC: H01G4/33 ,  H01L29/92 ,  H01L21/02 ,  H01L23/522

    Abstract: The integrated component has a number of conductor paths (13) and a capacitor (12) with a dielectric layer (5) between 2 electrode layers (14,15), which together are provided using the same sequence of metallisation layers (3,4,7-11) as that for the adjacent conductor path. The capacitor electrode layers may each be coupled to an underlying or overlying metal conductor path layer via a perpendicular connection (2,16), e.g. formed in an underlying intermediate dielectric layer (1).

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